Hello, I am new to the LPC2400 family so please bare in mind that I might be wrong! When configuring my PLL, I noticed that the data sheet for the LPC2478 states, when describing the layout of the CCLKCFG register, that:
7:0 CCLKSEL Selects the divide value for creating the CPU clock (CCLK) from the PLL output. Only 0 and odd values (1, 3, 5, ..., 255) are supported and can be used when programming the CCLKSEL bits. Warning: Using an even value (2, 4, 6, ..., 254) when setting the CCLKSEL bits may result in incorrect operation of the device.
But the default startup file provided by Keil sets the value of CCLKCFG_Val to 4.
You are correct. NXP has added this info into the user manual at some point (this info was not present in the early datasheets).
We haven't really seen problems on real HW when using some even values for CCLKSEL but as NXP says only odd values should be used for CCLKSEL.
LPC2400 startup file will be updated in the next MDK release.
Glad I could help.
If you're setting the CCLKSEL with the Configuration Wizard, the default value is not wrong. It's the wizard that's wrong (or at least confusing).
If you look at LPC2400.s with a text editor, you'll find:
;// <h> CPU Clock Configuration Register (CCLKCFG) ;// <o4.0..7> CCLKSEL: Divide Value for CPU Clock from PLL ;// <1-256><#-1> ;// </h> ... CCLKCFG_Val EQU 0x00000003
It subtracts one from the value set. For me, the wizard says 4, but CCLKSEL is defined as 3.
The Configuration Wizard is not wrong. It shows the actual divider value rather then the value which is written into the CCLKSEL filed. When divider value 4 is displayed then the actual value written into CCLKSEL is 3.
In some LPC2400.s files the default value of CCLKSEL was 4 (see bellow) and this was wrong. It is fixed now.
CCLKCFG_Val EQU 0x00000004