Hello,
Besides an RTX task polling, is there any glue that interconnects an FIQ with an RTX task?
Details below and thank you for your help, Lonnie
Details I have a peripheral driver (ARM Cortex) that is asynchronous and triggers an FIQ when it receives data. The FIQ analyzes the data (checks to see if it had received the correct closing sequence). Now, somehow I need to inform an RTX task that the complete set of data has been received.
Since FIQ cannot call RTX functions, how can I inform the task that there is data ready? I can only think of polling.
Unless, there is some way to mate an RTX software interrupt to the peripheral?
I guess you better ask Keil support or consult the RTX manual for your target. I don't know your chip (yet).
ARM Cortex-M3 (ST STM32) According to the > RL-RTX > Theory of Operation > Interrupt Functions -You cannot call the isr_ library functions from the FIQ interrupt function. www.keil.com/.../rlarm_ar_inter_funct.htm
With this in mind, I could have a task pole for a bit
/* global bit that is poled for completion */ volatile BIT bRcvdMsg = __FALSE; void USART1_IRQHandler(void) { /* do some message checking here and if ** ok - then inform the task by setting a bit */ bRcvdMsg = __TRUE; } __task void taskUSARTPollingTask( void ) { for(;;) { /* Just wait for a complete message to be received to inform ** the RS232 Handler Task */ if(bRcvdMsg == __TRUE) /* Inform the RS232 Handler Task */ isr_evt_set ( EM_DSP_USART_RCVD , g_taskCLI); os_dly_wait (20); } }
--- OR ---
May be use SVC Functions or SWI Functions to map to the interrupt handler? Then use that to trigger the task. I haven't really seen this done in a task where they were using the RTX (at least not for the IC I am using). Any ideas?
Sorry - In the previous message, please replace isr_evt_set() with os_evt_set()
if(bRcvdMsg == __TRUE) /* Inform the RS232 Handler Task */ isr_evt_set ( EM_DSP_USART_RCVD , g_taskCLI);
here you are trying to use the isr_evt_set function from user mode. that won't work. why do you need a FIQ? can't you put up with a high priority IRQ?
Oops, you corrected yourself already. But my second comment stands: why not IRQ?
What about:
1 - FIQ does it's processing and detects 'completion' 2 - On completion, FIQ triggers a software generated IRQ 3 - IRQ does nothing except call isr_evt_set
I'm not familiar with your processor, but I have done this very same sequence successfully on an STR9.
There is no FIQ in Cortex-M, so there is no such problem. The core peripheral NVIC is used to generate exceptions. It is safe to use isr_xxx functions from the exception handlers.
Thank you for all the responses!! (Sorry for the long wait - I have been on vacation)
Good news, the problem is fixed.
With all the comments, I focused on the code again and realized the functionality I was performing inside the interrupt was causing the problem. Not the isr function call from the IRQ.
Thanks again for all your help!!