I've made a memory mapped 8051 design using the AT89S52. Connected to the AT89S52 are two external memories.
The memories are located at:
Address 0x0000 = Parallel EEPROM Address 0x2000 = Parallel SRAM
I've defined the SRAM as off-chip xdata memory and it is working fine.
How should I define the EEPROM to be able to access it as off-chip non-volatile memory AND/OR expanded code memory?
is the EEPROM fast enough for both read and write?
otherwise both will be XDATA and all you have to do is to modify startup.a51 not to erase the permanent storage.
Erik
Hi Erik,
EEPROM = AT28C64B SRAM = CY6264
I must have read and write access to the EEPROM. The EEPROM read cycle is fast enough but the write cycle is slow (10ms).
1.) How should I define the EEPROM to be able to access it as off-chip non-volatile memory AND/OR expanded code memory? 2.) How do I write to the EEPROM with this slow write cycle? A delay after each write? 3.) If both the EEPROM and SRAM is defined as XDATA, how will I distinguish between the variables between the two different memory types? Absolute addressing?
Ok. I had an issue that was the reason for this post. I did however solve the problem in the mean time.
The problem was that the Software Data Protection (SDP) was enabled causing the EEPROM not to respond as I expected.
I defined the EEPROM as an XDATA memory and can read and write to it. I do allow a write cycle time (10ms) after a write.
I do have one remaining question. It is not Keil specific but will appreciate if you guys could help.
When the AT89S52 fetch code instructions from external code memory (Such as the Parallel EEPROM), do the EEPROM have to be located at 0x0000?
Sorry, let me re-phrase. If the AT89S52 is configured to fetch program instructions from an external memory (EA = 0), do that memory have to be located at 0x0000?
I am not familiar with the AT89S52 device and I don't have time to fetch the data sheets. If the device has on chip EPROM and you plan to use both on-chip and external EPROM then the external EPROM is not required to start at 0x0000. Read the data sheet on the /PSEN strobe. Assume that you had 4K of on chip EPROM. Any MOVC instruction will activate the /PSEN AFTER the 4K boundry so your external EPROM address could start at 0x0000 but you will lose the first 4K of the external EPROM. But the answer to you immediate question is "YES", you must have code located at 0x0000. Any reset will attempt to execute code at this location. If you leave the external EPROM as XDATA then you cannot fetch instructions from XDATA. So you must make your external EPROM memory appear as von Neumann memory which means you must use external glue logic to logical OR the /PSEN and /RD strobes. With your stated XDATA EPROM you cannot execute code from the external EPROM.
And I know some devices have this ability that you can select via special function registers. I do not know if the AT89S52 has this structure.
Search this forum for "The Bible of 8051 basic operations. There are lot of good links with examples. Also, search http://www.8052.com for great info on this topic. Bradford