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Cannot program 2 boards with any ULINK2

N P

Hello

I have 2 ULINK2 USB-JTAG Adapters and two MCBSTR9 Keil Boards. The former has a STR12FW44 MCU (Vers.3) and the latter a STR912FAW44 (Vers.4). I cannot program Flash memory in any board using any adapter. Messages I obtain are:

Error: Flash Download failed - ARM966E-S   or
Could not stop ARM device. Please check the JTAG cable.

First I though my project was badly configured, but I have spend some days checking it and I can't find where my error is. I've worked with ULINK and I never had problems to download my code.

Currently I'm using a licensed copy of uVision3 with MDK-ARM Version 3.22a. My configuration settings are:

Device: STR12FW44 or STR12FAW44 (I think it makes no difference).
Read/Only memory areas IROM1 checked (startup) address range: 0x0 - 0x88000

Debug settings: ULINK ARM Debugger. Use reset at startup, Verify Code Download, Download to Flash. ULINK 2 Firmware version is 1.36 and JTAG clock is 1MHz. By the way, ULIN2 is correctly listed as HID in PC hardware settings.

Driver for Flash programming: Update Target before debugging checked. Algorithm: STR91xFxx4 Flash Bank 0 (512K, starting at 0x000000): Erase sectors, Program, Verify and Reset and Run.

Perhaps I gave too much information, but I'm stalled and I don't know what to do. ¿Maybe is Flash corrupted?.

Any help would be appreciated. Thank you.

Parents
  • 0 in reply to Catcus Blip

    Hello Tamir.
    I've tried to erase full Flash following the instructions linked above by Martin. Is there another way to do that from uVision?

    PLL configuration is the same as in Http Demo example. Master clock is derived from PLL, and it's value is 96MHz. I can change it to 48Mhz, but that would be still derived from PLL. Flash Memory Interface Clock (FMICLK) is RCLK divided by 2. Which in turns is Master clock divided by 2. So, in short:

    fMSTR = fPLL = 96MHz
RCLK = fMSTR / 2 = 48MHz
FMICLK = RCLK / 2 = 24MHz

    (now is when I miss my tiny 8051)

    Should I change something in that configuration?. And if the problem was in PLL configuration... doesn't a simpler project as Blinky (who's master clock is 48MHz) should work?

    Thank you.

Reply
  • 0 in reply to Catcus Blip

    Hello Tamir.
    I've tried to erase full Flash following the instructions linked above by Martin. Is there another way to do that from uVision?

    PLL configuration is the same as in Http Demo example. Master clock is derived from PLL, and it's value is 96MHz. I can change it to 48Mhz, but that would be still derived from PLL. Flash Memory Interface Clock (FMICLK) is RCLK divided by 2. Which in turns is Master clock divided by 2. So, in short:

    fMSTR = fPLL = 96MHz
RCLK = fMSTR / 2 = 48MHz
FMICLK = RCLK / 2 = 24MHz

    (now is when I miss my tiny 8051)

    Should I change something in that configuration?. And if the problem was in PLL configuration... doesn't a simpler project as Blinky (who's master clock is 48MHz) should work?

    Thank you.

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