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PROBLEM IN TRIGERRING CYPRESS GPIF

vanitha kutti

hello, I am developing a cypress FX2 firmware to interface it with FIFO in FPGA. iam using GPIF master mode. I have downloaded cyconsole to test my firm ware
. i have generated the control signals using the GPIF tool. i am able todownload the firm ware and check the statue of the FIFO , GPIF ( for idle
) and EP2 (out) using the vendor commands . when a send the data from tnehost to EP2 for triggering a write transation , the statue of EP2 is notempty which means there is some data . the atatue of the FIFO is empty and Gpif status is idle . but when i read the GPIFTRIG status it is not triggered for thewrite transation. so write cycle is not initiated . iamnot able to write data into my FIFO. all the conditions are satisfied andthen also the GPIF is not trigerred for fifo write . can any one help? the firm ware also contains the coding for triggering . HERE IS THE CODING IN KEIL C

void TD_Init(void)             // Called once at startup
{
  // set the CPU clock to 48MHz
  CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
  SYNCDELAY;
  EP2CFG = 0xA0;
  SYNCDELAY;
  EP4CFG = 0x00;
  SYNCDELAY;
  EP6CFG = 0xE0;
  SYNCDELAY;
  EP8CFG = 0x00;
  SYNCDELAY;
  FIFORESET = 0x80;
  SYNCDELAY;
  FIFORESET = 0x02;
  SYNCDELAY;
  FIFORESET = 0x06;
  SYNCDELAY;
  FIFORESET = 0x00;
  SYNCDELAY;
  EP2FIFOCFG = 0x01;
  SYNCDELAY;
  EP2FIFOCFG = 0x11;
  SYNCDELAY;
  EP6FIFOCFG = 0x09;
  SYNCDELAY;
  GpifInit (); // initialize GPIF registers
  SYNCDELAY;
  EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses EF flag
  SYNCDELAY;
  EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses FF flag
  SYNCDELAY;
}

void TD_Poll(void)
{
  if( GPIFTRIG & 0x80 )               // if GPIF interface IDLE
  {
    if ( ! ( EP24FIFOFLGS & 0x02 ) )  // if there's a packet in the peripheral domain for EP2
        {
      if ( GPIFREADYSTAT&0x02  )           // if the external FIFO is not full EXTFIFONOTFULL
          {
            if(enum_high_speed)
                {
              SYNCDELAY;
          GPIFTCB1 = 0x01;            // setup transaction count (512 bytes/2 for word wide -> 0x0100)
          SYNCDELAY;
          GPIFTCB0 = 0x00;
          SYNCDELAY;
                }
                else
                {
                  SYNCDELAY;
                  GPIFTCB1 = 0x00;            // setup transaction count (64 bytes/2 for word wide -> 0x20)
          SYNCDELAY;
                  GPIFTCB0 = 0x20;
                  SYNCDELAY;
                }
         //   Setup_FLOWSTATE_Write();      // setup FLOWSTATE registers for FIFO Write operation
      //  SYNCDELAY;
        GPIFTRIG = GPIF_EP2;          // launch GPIF FIFO WRITE Transaction from EP2 FIFO
        SYNCDELAY;

            while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
        {
          ;
        }
        SYNCDELAY;
          }
    }
  }

thanks
punitha

0