I can understand that during ANL or ORL operations at bit level, there won't be any change with the status flags of the PSW.
However, if a CPL or CLR or SETB operation is performed on one of the addressable bits of the Accumulator (e.g. SETB 0E3h) and if the result of that operation changes the number of 1's in the accumulator, shouldn't that cause a change in the status of the Parity flag of the PSW?
I'd presume that a similar case could be made for the operation MOV 0E5h,C resulting in a change in the number of 1's of the accumulator?
Any instruction that modifies the ACC will condition the P flag - Note that I said condition, and not change.
So ANL, ORL, CPL, CLR, SETB, MOV (and any I've not included) that affect the ACC, will condition the P flag.
Refer to the bible for details.
OK, thanks! I was asking the question, because if you refer to the page:
http://www.keil.com/support/man/docs/is51/is51_clr.htm
and look at the "CLR bit" instruction, it was a little misleading to see that the possibility of the Parity flag likely to be "conditioned", as you say, was not indicated in the status of the PSW shown...