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Status flags during bit-level operations

Vinay Ramyead

I can understand that during ANL or ORL operations at bit level, there won't be any change with the status flags of the PSW.

However, if a CPL or CLR or SETB operation is performed on one of the addressable bits of the Accumulator (e.g. SETB 0E3h) and if the result of that operation changes the number of 1's in the accumulator, shouldn't that cause a change in the status of the Parity flag of the PSW?

I'd presume that a similar case could be made for the operation MOV 0E5h,C resulting in a change in the number of 1's of the accumulator?

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