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STM32 and ITM Viewer

Raphael L�ffel

I'am using the STM32 and tried to use the ITM-Viewer. At the Keil documentation "Using the ITM Viewer" is a code example of the fputc() function.

int fputc(int ch, FILE *f) {
  if (DEMCR & TRCENA) {
    while (ITM_Port32(0) == 0);
    ITM_Port8(0) = ch;
  }
  return(ch);
}

This function call will end at a hardware fault. The check if the trace is activated ( if (DEMCR & TRCENA) { )seems to be the source of this hardware fault. If I keep a way this check the ITM Viewer is working fine. Does anybody know, if I have to be at privileged mode to have access to the DEMCR register?

Thanks for help.

  • 0

    CPU can access DEMCR (Debug Exception and Monitor Control Register) only from Privileged Mode just like you assumed.

    You can omit the checking if Trace is activated via DEMCR in order to use Unprivileged Mode however then this code will hang when the debugger is not connected.

    The reference example runs when debugger is connected or not (and it runs in Privileged Mode).

  • 0 in reply to Robert  

    Thanks for the feedback. Because I'am running at unpreveleged mode I'will omit that the Tracer is working as you recommended.

    Do you have an idee were this behaviour is documented ( for example a list with all the registers which are only accesable at priviledeg mode )? I wasn't able to figure it out, out of the STM32 debug section of the reference manual.

  • 0 in reply to Raphael L�ffel

    Behavior of Cortex-M3 core registers is described in the cortex-M3 TRM (provided by ARM).

    In reality all registers in the PPB (Private Peripheral Bus) allow only privileged access. Those registers are from 0xE0000000 to 0xE00FFFFF and include ITM, DWT, FPB, SCS (NVIC, MPU ...), TPIU, ETM.

    Only a few registers can be accessed from unprivileged mode like ITM where all registers can be read and Stimulus Ports can be written (conditionally also Trace Enable can be written). Also SW Trigger Interrupt (in NVIC) can be written from unprivileged mode if enabled in the Configuration Control Register.