Hello, I am mapping interrupts to RAM (MEMMAP = 2). I want to overwrite some of the contents of 0x40000000 with my own address (namely, 0x40000008, that is the SWI handler). I know what I want: I need to install a branch instruction like
LDR PC, SWI_Handler
But when I look at address 0x0 (just for an example of how it is done in flash), I see the following repeating pattern:
0x0 18F09FE5 0x4 18F09FE5 0x8 18F09FE5 0xC 18F09FE5
I would expect to find there different instructions! What gives?
I don't know much about this.
But I "guess", maybe it is due to that, you do not implement the related xxxx_Handler. So KEIL just simply optimizes them.
Undef_Handler B Undef_Handler SWI_Handler B SWI_Handler PAbt_Handler B PAbt_Handler DAbt_Handler B DAbt_Handler IRQ_Handler B IRQ_Handler FIQ_Handler B FIQ_Handler
hi, thanks. I see that the first 64 bytes are dedicated to "vectors" followed by "address handlers". I don't fully understand the difference between the two: when ordering the startup file to copy vectors to RAM, actually 64 bytes are copied - both. what is the difference between them? and if I want to update the address of a handler (hence in the second 32 bytes), what does that mean for the 32 bytes?
opps. I mean "I see that the first 32 bytes are dedicated to "vectors", followed by 32 bytes dedicated to addresses of handlers. the data sheet is not very clear (LPC2000)...
ok, I solved it. placed my custom SWI address at 0x40000028, and copied the first 32 bytes as they are! thanks anyway.
Note that you need to copy 64 bytes to RAM when remapping vectors. the address handlers are placed in the second half of that region. I guess you are using an operating system like RTX; if so, do note that RTX calls are carried out using SWI calls, so if you remap interrupts before initializing RTX, you must make sure that the image of RTX places its own SWI handler in RAM. it seems that is what you have done.
> But I "guess", maybe it is due to that, you do not > implement the related xxxx_Handler. So KEIL just > simply optimizes them.
I was stupid. Though I haven't become smarter, I get better understanding about the exception handlers.
The machine code 18F09FE5 (E59FF018) means LDR PC, [PC, #0x0018] This is a "PC - relative addressing".
Each triggered exception handler has a different PC value, so the processor will fetch a different instruction from a different address.
For example:
Vectors LDR PC, Reset_Addr LDR PC, Undef_Addr LDR PC, SWI_Addr LDR PC, PAbt_Addr LDR PC, DAbt_Addr NOP ; Reserved Vector LDR PC, [PC, #-0x0120] ; Vector from VicVectAddr LDR PC, FIQ_Addr
Reset_Addr at 0x00000000 is an instruction -> LDR PC, [PC, #0x0018] After it is executed, it will load the content of address (0x0000 + 0x4 + 0x4 + 0x0018) 0x0020 into PC. In my case, the content of address 0x0020 is 0x0054, So the value of Program Counter will become 0x0054.
> Reset_Addr at 0x00000000 is an instruction -> LDR PC, [PC, #0x0018]
Reset Handler at 0x00000000 is an instruction -> LDR PC, [PC, #0x0018]