This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

What optimizations should be expected from a C compiler for small uPs?

My knowledge of current compiler optimization technology is very limited (or ancient).
Am familiar with VHDL and Verilog for FPGA chips where extreme optimization is typical (dead code removal, code duplication to meet performance constraints, morphing from the language constructs into available hardware constructs).

In the context of the large variety of small microprocessors (of 8, 16 or 32 bits), each with unique peripheral collections; what would raise the coding to higher levels of abstraction, given one is still dealing with IO ports and peripherals?

0