What is the difference of a SWI and a Hardwareinterrupt?
For example if code toggles a port which is connected to a IRQ.
This question is the essence of my formerly thread. Hope there will be some posetive echo. :-)
Hi Tamir,
I think you are right. The point is that when you are in supervisor mode (SWI) you are protected from further interruptions. This is essential for the use of SWI as non preemtive environment. Every processor implementation is a bit different - its hard to know them all in detail.
Frank
The ARM processor itself has an SWI interrupt, where you run a specific instruction to switch into supervisor mode (SVC) and where the processor can not be interrupted. I.e. basically a way of creating "critical sections" in the code.
To confuse it a bit, the processor you are using have registers with SWI in their name but with the function that they allow the software to manually trig a hardware interrupt. You set a flag, and the processor will then notice a pending interrupt and activate it when allowed.
In your case, you get two different concepts both using the SWI term. The NXP processors do not call the manually activated interrupts SWI. On the LPC23xx chips, the register is called VICSoftInt.
In the end, you get the situation that you have the swi processor instruction to generate software interrupts into SVC mode. They form an interrupt-safe critical section, and you can send parameters and get back a return value.
And you have the SWISRC register that lets the software trig a "normal" interrupt and where FIQ can break in in the middle. No parameters can be sent or returned since SWISRC creates an asynchronous interrupt.