What is the difference of a SWI and a Hardwareinterrupt?
For example if code toggles a port which is connected to a IRQ.
This question is the essence of my formerly thread. Hope there will be some posetive echo. :-)
And I also managed to give a bit of an answer in your previous thread - before seeing this question :)
a SWI is a software interrupt; the instruction SWI (with optional parameter) causes the processor to branch to a special software handler. see your SWI.s file for details, and of course your documentation. a hardware interrupt often notifies the processor of a peripheral related event - a character coming in from a UART, for example - but has the same effect in the sense that the processor branches to a predetermined location. for the ARM9, this is 0x18, where the VIC is interrogated as to where the software should just next to handle the event.
Hi Georg,
SWI are implemented in more complex microprocessor systems to deal with the problems introduced by different priviledge levels of the processor. The SWI has normally the highest priority of all external trigerred exceptions (i.e. IRQ, FIQ for ARM) but lower than processor related exceptions. Calling software routines from different priviledge levels requires these functions to be reentrant. But this is not enough. Certain parts of functions need to be atomic to produce correct results. Imagine that you have a driver function and the access to this function is protected by a busy flag. Reading the flag and setting it to the state busy requires to be a atomic (non interruptable). There is no single processor command to do this, therefore you put the required code into a SWI function. When you enter the SWI function, no one can interrupt you - therefore the code inside the SWI function is atomic. By the way, did you notice that SWI interrupt functions allow you to send parameters and receive a return value. This is possibel since you are in control when and where the SWI is called. Hope this helps.
Frank
Hi Frank, thanks for your advice. befor your explanation i completely missunderstood SWI functionality. My reference was the ADuC7026 datasheet. Can you guide me to some better literature?
F D, SWI can be interrupted by a FIQ, if I remember correctly.
Hi Tamir,
I think you are right. The point is that when you are in supervisor mode (SWI) you are protected from further interruptions. This is essential for the use of SWI as non preemtive environment. Every processor implementation is a bit different - its hard to know them all in detail.
you can start with the Keil help system: - go in Search - type SWI - press search
The Keil help system is pretty good and gives you a lot of additional information. Start using it.
The ARM processor itself has an SWI interrupt, where you run a specific instruction to switch into supervisor mode (SVC) and where the processor can not be interrupted. I.e. basically a way of creating "critical sections" in the code.
To confuse it a bit, the processor you are using have registers with SWI in their name but with the function that they allow the software to manually trig a hardware interrupt. You set a flag, and the processor will then notice a pending interrupt and activate it when allowed.
In your case, you get two different concepts both using the SWI term. The NXP processors do not call the manually activated interrupts SWI. On the LPC23xx chips, the register is called VICSoftInt.
In the end, you get the situation that you have the swi processor instruction to generate software interrupts into SVC mode. They form an interrupt-safe critical section, and you can send parameters and get back a return value.
And you have the SWISRC register that lets the software trig a "normal" interrupt and where FIQ can break in in the middle. No parameters can be sent or returned since SWISRC creates an asynchronous interrupt.