Hi guys I started working on AT89C51RE2 as it has 2 serial ports - as per my requirement however I couldn't find header file for the same the one which is available for RE2 on keil.com is actually of RD2 so no special SFRs for 2 UARTs. I put my own UARTs with the help of SFRs table from datasheet but is it possible to download header file for RE2? If not can anybody check my header file please. And if its correct can I upload it here for further usage?
Then why is it given in the datasheet that way I've AT89c51re2 datasheet where above locations are shown as bit addressable or I mustn't have read it well I'll read it again - more carefully but I'm sure that these location are given as the way bit addressable locations are given
Sorry Andy you are correct I just read it till the end of SFRs and didn't notice the next page - the information is given bit addressable way however they are not bit addresssable
Sorry guys but as Andy said the location(SFRs) which are not ending with 0 or 8 are not bit addressable . I'll change my headerfile that way anyway. should I post it again or is it ok that way here in this post
Since there are so many such changes, it'd probab;y be worth reposting - it'll make the file much shorter!
:-)
For bit addressable SFRs I have two defines: bit and mask
I use TCON as an example sbit B_TCON_TF1 = 8x8f #dfine M_TCON_TF1 0x80
For NON bit addressable SFRs I have one define: mask
I use TMOD as an example #dfine M_TMOD T0M1 0x02
I know that it is not customary to include the SFR name in bitdefs; I, however find it a great advantage.
jhere is an extract from on of my files (LPC93x)
sfr SF_TCON = 0x88; sbit SB_TCON_IT0 = 0x88; #define SM_TCON_IT0 0x01 sbit SB_TCON_IE0 = 0x89; #define SM_TCON_IE0 0x02 sbit SB_TCON_IT1 = 0x8A; #define SM_TCON_IT1 0x04 sbit SB_TCON_IE1 = 0x8B; #define SM_TCON_IE1 0x08 sbit SB_TCON_TR0 = 0x8C; #define SM_TCON_TR0 0x10 sbit SB_TCON_TF0 = 0x8D; sbit SB_TCON_TR1 = 0x8E; #define SM_TCON_TR1 0x40 sbit SB_TCON_TF1 = 0x8F; sfr SF_TMOD = 0x89; #define SM_TMOD_T1CLR 0x0f #define SM_TMOD_T0TM1 0x01 #define SM_TMOD_T0CM1 0x05 // T0 as 16 bit counter #define SM_TMOD_T0CLR 0xf0 #define SM_TMOD_T1TM1 0x10 #define SM_TMOD_T1TM2 0x20
you will see that I have gone one step further and instead of M0 and M1 I define the actual modes.
The advantage if this definition practice is that any search on a SFRname gives ALL access to that SFR and any search on a bit name gives ALL access to that bit whether by sbit, clr, anl, orl, mov ....
This originated from many debuggiung sessions where some use of a bit was 'hidden' e.g. mov TCON, 004h.
Erik
Thanks a lot Andy I've removed all the wrong bit addressable definitions. I am posting that file And Erik frankly I didn't understand your post I guess I'll have to work on it
Here is the updated file its was quite hasty but i hope i've done it correctly
/************************************************************************************** * NAME : AT89C51RE2.H --------------------------------------------------------------------------------------- *PURPOSE : SFR Description file for atmel at89c51re2 product (uC) on KEIL compiler --------------------------------------------------------------------------------------- *DATE : April 1st, 2008 * VERSION : 1.0 --------------------------------------------------------------------------------------- *AUTHOR : Pratik Mahajan ***************************************************************************************/ #ifndef _AT89C51RE2_H #define _AT89C51RE2_H #define Sfr(x, y) sfr x = y #define Sbit(x, y, z) sfr x = y^z #define Sfr16(x,y) sfr16 x = y /*------------------------------------------------------------------------------------*/ /*---------------------------SFR Definitions------------------------------------------*/ /*------------------------------------------------------------------------------------*/ /* C51 Core Registers */ Sfr (ACC, 0xE0); Sfr (B, 0xF0); Sfr (PSW, 0xD0); /* PSW :- bit addressing */ Sbit (CY, 0xD0, 7); Sbit (AC, 0xD0, 6); Sbit (F0, 0xD0, 5); Sbit (RS1, 0xD0, 4); Sbit (RS0, 0xD0, 3); Sbit (OV, 0xD0, 2); Sbit (F1, 0xD0, 1); Sbit (PAR, 0xD0, 0); Sfr (SP, 0x81); Sfr (DPL, 0x82); Sfr (DPH, 0x83); /* System Management SFRs */ Sfr (PCON, 0x87); Sfr (AUXR, 0x8E); Sfr (AUXR1,0xA2); Sfr (CKRL, 0x97); Sfr (BMSEL, 0x92); Sfr (CKCON0, 0x8F); Sfr (CKCON1, 0xAF); /* Interrupt SFRs */ Sfr (IEN0, 0xA8); Sbit (EA, 0xA8, 7); Sbit (EC, 0xA8, 6); Sbit (ET2, 0xA8, 5); Sbit (ES, 0xA8, 4); Sbit (ET1, 0xA8, 3); Sbit (EX1, 0xA8, 2); Sbit (ET0, 0xA8, 1); Sbit (EX0, 0xA8, 0); Sfr (IEN1, 0xB1); Sfr (IPH0, 0xB7); Sfr (IPL0, 0xB8); Sbit (PPCL, 0xB8, 6); Sbit (PT2L, 0xB8, 5); Sbit (PSL, 0xB8, 4); Sbit (PT1L, 0xB8, 3); Sbit (PX1L, 0xB8, 2); Sbit (PT0L, 0xB8, 1); Sbit (PX0L, 0xB8, 0); Sfr (IPH1, 0xB3); Sfr (IPL1, 0xB2); /* PORT SFRs */ Sfr (P0, 0x80); Sbit (P0_7, 0x80, 7); Sbit (P0_6, 0x80, 6); Sbit (P0_5, 0x80, 5); Sbit (P0_4, 0x80, 4); Sbit (P0_3, 0x80, 3); Sbit (P0_2, 0x80, 2); Sbit (P0_1, 0x80, 1); Sbit (P0_0, 0x80, 0); Sfr (P1, 0x90); Sbit (P1_7, 0x90, 7); Sbit (P1_6, 0x90, 6); Sbit (P1_5, 0x90, 5); Sbit (P1_4, 0x90, 4); Sbit (P1_3, 0x90, 3); Sbit (P1_2, 0x90, 2); Sbit (P1_1, 0x90, 1); Sbit (P1_0, 0x90, 0); Sfr (P2, 0xA0); Sbit (P2_7, 0xA0, 7); Sbit (P2_6, 0xA0, 6); Sbit (P2_5, 0xA0, 5); Sbit (P2_4, 0xA0, 4); Sbit (P2_3, 0xA0, 3); Sbit (P2_2, 0xA0, 2); Sbit (P2_1, 0xA0, 1); Sbit (P2_0, 0xA0, 0); Sfr (P3, 0xB0); Sbit (P3_7, 0xB0, 7); Sbit (P3_6, 0xB0, 6); Sbit (P3_5, 0xB0, 5); Sbit (P3_4, 0xB0, 4); Sbit (P3_3, 0xB0, 3); Sbit (P3_2, 0xB0, 2); Sbit (P3_1, 0xB0, 1); Sbit (P3_0, 0xB0, 0); Sfr (P4, 0xC0); Sbit (P4_7, 0xC0, 7); Sbit (P4_6, 0xC0, 6); Sbit (P4_5, 0xC0, 5); Sbit (P4_4, 0xC0, 4); Sbit (P4_3, 0xC0, 3); Sbit (P4_2, 0xC0, 2); Sbit (P4_1, 0xC0, 1); Sbit (P4_0, 0xC0, 0); Sfr (P5, 0xE8); Sbit (P5_7, 0xE8, 7); Sbit (P5_6, 0xE8, 6); Sbit (P5_5, 0xE8, 5); Sbit (P5_4, 0xE8, 4); Sbit (P5_3, 0xE8, 3); Sbit (P5_2, 0xE8, 2); Sbit (P5_1, 0xE8, 1); Sbit (P5_0, 0xE8, 0); Sfr (P6, 0xF8); Sbit (P6_1, 0xF8, 1); Sbit (P6_0, 0xF8, 0); /* Flash & EEPROM data Memory SFR */ Sfr (FCON, 0xD1); Sfr (FSTA, 0xD3); /* Timer SFRs */ Sfr (TCON, 0x88); Sbit (TF1, 0x88, 7); Sbit (TR1, 0x88, 6); Sbit (TF0, 0x88, 5); Sbit (TR0, 0x88, 4); Sbit (IE1, 0x88, 3); Sbit (IT1, 0x88, 2); Sbit (IE0, 0x88, 1); Sbit (IT0, 0x88, 0); Sfr (TMOD, 0x89); Sfr (TL0, 0x8A); Sfr (TH0, 0x8C); Sfr (TL1, 0x8B); Sfr (TH1, 0x8D); Sfr (WDTRST, 0xA6); Sfr (WDTPRG, 0xA7); Sfr (T2CON, 0xC8); Sbit (TF2, 0xC8, 7); Sbit (EXF2, 0xC8, 6); Sbit (RCLK, 0xC8, 5); Sbit (TCLK, 0xC8, 4); Sbit (EXEN2, 0xC8, 3); Sbit (TR2, 0xC8, 2); Sbit (C/T2, 0xC8, 1); Sbit (CP/RL2, 0xC8, 0); Sfr (T2MOD, 0xC9); Sfr (RCAP2H, 0xCB); Sfr (RCAP2L, 0xCA); Sfr (TH2, 0xCD); Sfr (TL2, 0xCC); /* PCA SFRs */ Sfr (CCON, 0xD8); Sbit (CF, 0xD8, 7); Sbit (CR, 0xD8, 6); Sbit (CCF4, 0xD8, 4); Sbit (CCF3, 0xD8, 3); Sbit (CCF2, 0xD8, 2); Sbit (CCF1, 0xD8, 1); Sbit (CCF0, 0xD8, 0); Sfr (CMOD, 0xD9); Sfr (CL, 0xE9); Sfr (CH, 0xF9); Sfr (CCAPM0, 0xDA); Sfr (CCAPM1, 0xDB); Sfr (CCAPM2, 0xDC); Sfr (CCAPM3, 0xDD); Sfr (CCAPM4, 0xDE); Sfr (CCAP0H, 0xFA); Sfr (CCAP1H, 0xFB); Sfr (CCAP2H, 0xFC); Sfr (CCAP3H, 0xFD); Sfr (CCAP4H, 0xFE); Sfr (CCAP0L, 0xFA); Sfr (CCAP1L, 0xEB); Sfr (CCAP2L, 0xEC); Sfr (CCAP3L, 0xED); Sfr (CCAP4L, 0xFE); /* Serial I/O Port SFRs */ Sfr (SCON_0, 0x98); Sbit (FE/SM0_0, 0x98, 7); Sbit (SM1_0, 0x98, 6); Sbit (SM2_0, 0x98, 5); Sbit (REN_0, 0x98, 4); Sbit (TB8_0, 0x98, 3); Sbit (RB8_0, 0x98, 2); Sbit (TI_0, 0x98, 1); Sbit (RI_0, 0x98, 0); Sfr (SBUF_0, 0x99); Sfr (SADEN_0, 0xB9); Sfr (SADDR_0, 0xA9); Sfr (BDRCON_0, 0x9B); Sfr (BRL_0, 0x9A); Sfr (SCON_1, 0xC0); Sbit (FE/SM0_1, 0xC0, 7); Sbit (SM1_1, 0xC0, 6); Sbit (SM2_1, 0xC0, 5); Sbit (REN_1, 0xC0, 4); Sbit (TB8_1, 0xC0, 3); Sbit (RB8_1, 0xC0, 2); Sbit (TI_1, 0xC0, 1); Sbit (RI_1, 0xC0, 0); Sfr (SBUF_1, 0xC1); Sfr (SADEN_1, 0xBA); Sfr (SADDR_1, 0xAA); Sfr (BDRCON_1, 0xBC); Sfr (BRL_1, 0xBB); /* SPI controller SFRs */ Sfr (SPCON, 0xC3); Sfr (SPSCR, 0xC4); Sfr (SPDAT, 0xC5); /* Keyboard Interface SFRs */ Sfr (KBLS, 0x9C); Sfr (KBE, 0x9D); Sfr (KBF, 0x9E); #endif