Header file for AT89C51RE2

i had the same prob and editid a heder file. it was good but bug in compiler stops it working. the file was long but the error was at the start.
you can plz look at my one and see why the compiler is not round in the error.

Pratik,
How can we review something we cannot see? By the way, the last time I asked somebody here to review my stuff (it was a lot more that a header file, believe me :) ) there was only one saint that heeded. now, since there are very few saints here (I am one of them, by the way) I would suggest that you try either:
* dig in your tool-chain again.
* follow the data sheet - make your own header file.
* become a saint.

That is very unlikely.

Far more likely is that there's a bug (error) in your header and/or elsewhere in your source code.

If you really have found a genuine bug in the compiler, then you should report it direct to Keil

post your headerfile

1) use spaces, NO TABS
2) use pre .... as seen above the entry window "Place source code source code between ....."
3) use cut-and-paste, do not retype into the post

also
post the error message(s) you get

Erik

and why the code is not d

"and why the code is not d"

Keil don't make any compilers for 'd' - only 'C'

Follow the easy instructions: www.danlhenry.com/.../keil_code.png

For fuller details, click the 'Tips for Posting Messages' link.

As Erik said - use spaces, not TABs for layout.

and don't forget to check it carefully in the 'Preview'...

no saints here...

Sorry I didn't post it because first I wanted to ask whether somebody will do it
Anyway thanks a lot for support here i'm posting my header file please go through it and if its useful please upload it so anybody else can use Thank you again

/**************************************************************************************
* NAME : AT89C51RE2.H
---------------------------------------------------------------------------------------
*PURPOSE : SFR Description file for atmel at89c51re2 product (uC)
                            on KEIL compiler
---------------------------------------------------------------------------------------
*DATE : April 1st, 2008                   * VERSION : 1.0
---------------------------------------------------------------------------------------
*AUTHOR : Pratik Mahajan
***************************************************************************************/

#ifndef _AT89C51RE2_H
#define _AT89C51RE2_H

#define Sfr(x, y)       sfr x = y
#define Sbit(x, y, z)    sfr x = y^z
#define Sfr16(x,y)      sfr16 x = y

/*------------------------------------------------------------------------------------*/
/*---------------------------SFR Definitions------------------------------------------*/
/*------------------------------------------------------------------------------------*/

/*                           C51 Core Registers                                       */

Sfr (ACC, 0xE0);
Sfr (B,   0xF0);
Sfr (PSW, 0xD0);
/*  PSW :- bit addressing  */
Sbit (CY,  0xD0, 7);
Sbit (AC,  0xD0, 6);
Sbit (F0,  0xD0, 5);
Sbit (RS1, 0xD0, 4);
Sbit (RS0, 0xD0, 3);
Sbit (OV,  0xD0, 2);
Sbit (F1,  0xD0, 1);
Sbit (PAR, 0xD0, 0);

Sfr (SP,  0x81);
Sfr (DPL, 0x82);
Sfr (DPH, 0x83);

/*                                 System Management SFRs                              */

Sfr (PCON, 0x87);

Sbit (SMOD1_0, 0x87, 7);
Sbit (SMOD0_0, 0x87, 6);
Sbit (POF, 0x87, 4);
Sbit (GF1, 0x87, 3);
Sbit (GF0, 0x87, 2);
Sbit (PD,  0x87, 1);
Sbit (IDL, 0x87, 0);

Sfr (AUXR, 0x8E);

Sbit (M0, 0x8E, 5);
Sbit (XRS2, 0x8E, 4);
Sbit (XRS1, 0x8E, 3);
Sbit (XRS0, 0x8E, 2);
Sbit (EXTRAM, 0x8E, 1);
Sbit (AO, 0x8E, 0);

Sfr (AUXR1,0xA2);

Sbit (EES, 0xA2, 7);
Sbit (SP9, 0xA2, 6);
Sbit (U2,  0xA2, 5);
Sbit (GF2, 0xA2, 3);
Sbit (DPS, 0xA2, 0);

Sfr (CKRL, 0x97);
Sfr (BMSEL, 0x92);

Sbit (MBO2, 0x92, 7);
Sbit (MBO1, 0x92, 6);
Sbit (MBO0, 0x92, 5);
Sbit (FBS2, 0x92, 2);
Sbit (FBS1, 0x92, 1);
Sbit (FBS0, 0x92, 0);

Sfr (CKCON0, 0x8F);

Sbit (WDX2, 0x8F, 6);
Sbit (PCAX2, 0x8F, 5);
Sbit (SIX2_0, 0x8F, 4);
Sbit (T2X2, 0x8F, 3);
Sbit (T1X2, 0x8F, 2);
Sbit (T0X2, 0x8F, 1);
Sbit (X2, 0x8F, 0);

Sfr (CKCON1, 0xAF);

Sbit (SIX2_1, 0xAF, 1);
Sbit (SPIX2, 0xAF, 0);

/*                                     Interrupt SFRs                                   */

Sfr (IEN0, 0xA8);

Sbit (EA,  0xA8, 7);
Sbit (EC,  0xA8, 6);
Sbit (ET2, 0xA8, 5);
Sbit (ES,  0xA8, 4);
Sbit (ET1, 0xA8, 3);
Sbit (EX1, 0xA8, 2);
Sbit (ET0, 0xA8, 1);
Sbit (EX0, 0xA8, 0);

Sfr (IEN1, 0xB1);

Sbit (ES_1, 0xB1, 3);
Sbit (ESPI, 0xB1, 2);
Sbit (ETWI, 0xB1, 1);
Sbit (EKBD, 0xB1, 0);

Sfr (IPH0, 0xB7);

Sbit (PPCH, 0xB7, 6);
Sbit (PT2H, 0xB7, 5);
Sbit (PSH,  0xB7, 4);
Sbit (PT1H, 0xB7, 3);
Sbit (PX1H, 0xB7, 2);
Sbit (PT0H, 0xB7, 1);
Sbit (PX0H, 0xB7, 0);

Sfr (IPL0, 0xB8);

Sbit (PPCL, 0xB8, 6);
Sbit (PT2L, 0xB8, 5);
Sbit (PSL,  0xB8, 4);
Sbit (PT1L, 0xB8, 3);
Sbit (PX1L, 0xB8, 2);
Sbit (PT0L, 0xB8, 1);
Sbit (PX0L, 0xB8, 0);

Sfr (IPH1, 0xB3);

Sbit (PSH_1, 0xB3, 3);
Sbit (SPIH,  0xB3, 2);
Sbit (IE2CH, 0xB3, 1);
Sbit (KBDH,  0xB3, 0);

Sfr (IPL1, 0xB2);

Sbit (PSL_1, 0xB2, 3);
Sbit (SPIL,  0xB2, 2);
Sbit (IE2CL, 0xB2, 1);
Sbit (KBDL,  0xB2, 0);

/*                                          PORT SFRs                                  */

Sfr (P0, 0x80);

Sbit (P0_7, 0x80, 7);
Sbit (P0_6, 0x80, 6);
Sbit (P0_5, 0x80, 5);
Sbit (P0_4, 0x80, 4);
Sbit (P0_3, 0x80, 3);
Sbit (P0_2, 0x80, 2);
Sbit (P0_1, 0x80, 1);
Sbit (P0_0, 0x80, 0);

Sfr (P1, 0x90);

Sbit (P1_7, 0x90, 7);
Sbit (P1_6, 0x90, 6);
Sbit (P1_5, 0x90, 5);
Sbit (P1_4, 0x90, 4);
Sbit (P1_3, 0x90, 3);
Sbit (P1_2, 0x90, 2);
Sbit (P1_1, 0x90, 1);
Sbit (P1_0, 0x90, 0);

Sfr (P2, 0xA0);

Sbit (P2_7, 0xA0, 7);
Sbit (P2_6, 0xA0, 6);
Sbit (P2_5, 0xA0, 5);
Sbit (P2_4, 0xA0, 4);
Sbit (P2_3, 0xA0, 3);
Sbit (P2_2, 0xA0, 2);
Sbit (P2_1, 0xA0, 1);
Sbit (P2_0, 0xA0, 0);

Sfr (P3, 0xB0);

Sbit (P3_7, 0xB0, 7);
Sbit (P3_6, 0xB0, 6);
Sbit (P3_5, 0xB0, 5);
Sbit (P3_4, 0xB0, 4);
Sbit (P3_3, 0xB0, 3);
Sbit (P3_2, 0xB0, 2);
Sbit (P3_1, 0xB0, 1);
Sbit (P3_0, 0xB0, 0);

Sfr (P4, 0xC0);

Sbit (P4_7, 0xC0, 7);
Sbit (P4_6, 0xC0, 6);
Sbit (P4_5, 0xC0, 5);
Sbit (P4_4, 0xC0, 4);
Sbit (P4_3, 0xC0, 3);
Sbit (P4_2, 0xC0, 2);
Sbit (P4_1, 0xC0, 1);
Sbit (P4_0, 0xC0, 0);

Sfr (P5, 0xE8);

Sbit (P5_7, 0xE8, 7);
Sbit (P5_6, 0xE8, 6);
Sbit (P5_5, 0xE8, 5);
Sbit (P5_4, 0xE8, 4);
Sbit (P5_3, 0xE8, 3);
Sbit (P5_2, 0xE8, 2);
Sbit (P5_1, 0xE8, 1);
Sbit (P5_0, 0xE8, 0);

Sfr (P6, 0xF8);

Sbit (P6_1, 0xF8, 1);
Sbit (P6_0, 0xF8, 0);

/*                                Flash & EEPROM data Memory SFR                                     */

Sfr (FCON, 0xD1);

Sbit (FPL3, 0xD1, 7);
Sbit (FPL2, 0xD1, 6);
Sbit (FPL1, 0xD1, 5);
Sbit (FPL0, 0xD1, 4);
Sbit (FPS,  0xD1, 3);
Sbit (FMOD2, 0xD1, 2);
Sbit (FMOD1, 0xD1, 1);
Sbit (FMOD0, 0xD1, 0);

Sfr (FSTA, 0xD3);

Sbit (FMR, 0xD3, 7);
Sbit (FSE, 0xD3, 2);
Sbit (FLOAD, 0xD3, 1);
Sbit (FBUSY, 0xD3, 0);

/*                                 Timer SFRs                                         */

Sfr (TCON, 0x88);

Sbit (TF1, 0x88, 7);
Sbit (TR1, 0x88, 6);
Sbit (TF0, 0x88, 5);
Sbit (TR0, 0x88, 4);
Sbit (IE1, 0x88, 3);
Sbit (IT1, 0x88, 2);
Sbit (IE0, 0x88, 1);
Sbit (IT0, 0x88, 0);

Sfr (TMOD, 0x89);

Sbit (GATE1, 0x89, 7);
Sbit (C/T1, 0x89, 6);
Sbit (M11, 0x89, 5);
Sbit (M01, 0x89, 4);
Sbit (GATE0, 0x89, 3);
Sbit (C/T0, 0x89, 2);
Sbit (M01, 0x89, 1);
Sbit (M00, 0x89, 0);

Sfr (TL0, 0x8A);
Sfr (TH0, 0x8C);
Sfr (TL1, 0x8B);
Sfr (TH1, 0x8D);
Sfr (WDTRST, 0xA6);
Sfr (WDTPRG, 0xA7);

Sbit (WTO2, 0xA7, 2);
Sbit (WTO1, 0xA7, 1);
Sbit (WTO0, 0xA7, 0);

Sfr (T2CON, 0xC8);

Sbit (TF2, 0xC8, 7);
Sbit (EXF2, 0xC8, 6);
Sbit (RCLK, 0xC8, 5);
Sbit (TCLK, 0xC8, 4);
Sbit (EXEN2, 0xC8, 3);
Sbit (TR2, 0xC8, 2);
Sbit (C/T2, 0xC8, 1);
Sbit (CP/RL2, 0xC8, 0);

Sfr (T2MOD, 0xC9);

Sbit (T2OE, 0xC9, 1);
Sbit (DCEN, 0xC9, 0);

Sfr (RCAP2H, 0xCB);
Sfr (RCAP2L, 0xCA);
Sfr (TH2, 0xCD);
Sfr (TL2, 0xCC);

Sfr (CCAP4H, 0xFE);

Sbit (CCAP4H7, 0xFE, 7);
Sbit (CCAP4H6, 0xFE, 6);
Sbit (CCAP4H5, 0xFE, 5);
Sbit (CCAP4H4, 0xFE, 4);
Sbit (CCAP4H3, 0xFE, 3);
Sbit (CCAP4H2, 0xFE, 2);
Sbit (CCAP4H1, 0xFE, 1);
Sbit (CCAP4H0, 0xFE, 0);

Sfr (CCAP0L, 0xFA);

Sbit (CCAP0L7, 0xEA, 7);
Sbit (CCAP0L6, 0xEA, 6);
Sbit (CCAP0L5, 0xEA, 5);
Sbit (CCAP0L4, 0xEA, 4);
Sbit (CCAP0L3, 0xEA, 3);
Sbit (CCAP0L2, 0xEA, 2);
Sbit (CCAP0L1, 0xEA, 1);
Sbit (CCAP0L0, 0xEA, 0);

Sfr (CCAP1L, 0xEB);

Sbit (CCAP1L7, 0xEB, 7);
Sbit (CCAP1L6, 0xEB, 6);
Sbit (CCAP1L5, 0xEB, 5);
Sbit (CCAP1L4, 0xEB, 4);
Sbit (CCAP1L3, 0xEB, 3);
Sbit (CCAP1L2, 0xEB, 2);
Sbit (CCAP1L1, 0xEB, 1);
Sbit (CCAP1L0, 0xEB, 0);

Sfr (CCAP2L, 0xEC);

Sbit (CCAP2L7, 0xEC, 7);
Sbit (CCAP2L6, 0xEC, 6);
Sbit (CCAP2L5, 0xEC, 5);
Sbit (CCAP2L4, 0xEC, 4);
Sbit (CCAP2L3, 0xEC, 3);
Sbit (CCAP2L2, 0xEC, 2);
Sbit (CCAP2L1, 0xEC, 1);
Sbit (CCAP2L0, 0xEC, 0);

Sfr (CCAP3L, 0xED);

Sbit (CCAP3L7, 0xED, 7);
Sbit (CCAP3L6, 0xED, 6);
Sbit (CCAP3L5, 0xED, 5);
Sbit (CCAP3L4, 0xED, 4);
Sbit (CCAP3L3, 0xED, 3);
Sbit (CCAP3L2, 0xED, 2);
Sbit (CCAP3L1, 0xED, 1);
Sbit (CCAP3L0, 0xED, 0);

Sfr (CCAP4L, 0xFE);

Sbit (CCAP4L7, 0xEE, 7);
Sbit (CCAP4L6, 0xEE, 6);
Sbit (CCAP4L5, 0xEE, 5);
Sbit (CCAP4L4, 0xEE, 4);
Sbit (CCAP4L3, 0xEE, 3);
Sbit (CCAP4L2, 0xEE, 2);
Sbit (CCAP4L1, 0xEE, 1);
Sbit (CCAP4L0, 0xEE, 0);

/*                              Serial I/O Port SFRs                                  */

Sfr (SCON_0, 0x98);

Sbit (FE/SM0_0, 0x98, 7);
Sbit (SM1_0, 0x98, 6);
Sbit (SM2_0, 0x98, 5);
Sbit (REN_0, 0x98, 4);
Sbit (TB8_0, 0x98, 3);
Sbit (RB8_0, 0x98, 2);
Sbit (TI_0, 0x98, 1);
Sbit (RI_0, 0x98, 0);

Sfr (SBUF_0, 0x99);
Sfr (SADEN_0, 0xB9);
Sfr (SADDR_0, 0xA9);
Sfr (BDRCON_0, 0x9B);

Sbit (BRR_0, 0x9B, 4);
Sbit (TBCK_0, 0x9B, 3);
Sbit (RBCK_0, 0x9B, 2);
Sbit (SPD_0, 0x9B, 1);
Sbit (SRC_0, 0x9B, 0);

Sfr (BRL_0, 0x9A);

Sfr (SCON_1, 0xC0);

Sbit (FE/SM0_1, 0xC0, 7);
Sbit (SM1_1, 0xC0, 6);
Sbit (SM2_1, 0xC0, 5);
Sbit (REN_1, 0xC0, 4);
Sbit (TB8_1, 0xC0, 3);
Sbit (RB8_1, 0xC0, 2);
Sbit (TI_1, 0xC0, 1);
Sbit (RI_1, 0xC0, 0);

Sfr (SBUF_1, 0xC1);
Sfr (SADEN_1, 0xBA);
Sfr (SADDR_1, 0xAA);
Sfr (BDRCON_1, 0xBC);

Sbit (BRR_1, 0xBC, 4);
Sbit (TBCK_1, 0xBC, 3);
Sbit (RBCK_1, 0xBC, 2);
Sbit (SPD_1, 0xBC, 1);
Sbit (SRC_1, 0xBC, 0);

Sfr (BRL_1, 0xBB);

/*                                SPI controller SFRs                                 */

Sfr (SPCON, 0xC3);

Sbit (SPR2, 0xC3, 7);
Sbit (SPEN, 0xC3, 6);
Sbit (SSDIS, 0xC3, 5);
Sbit (MSTR, 0xC3, 4);
Sbit (CPOL, 0xC3, 3);
Sbit (CPHA, 0xC3, 2);
Sbit (SPR1, 0xC3, 1);
Sbit (SPR0, 0xC3, 0);

Sfr (SPSCR, 0xC4);

Sbit (SPIF, 0xC4, 7);
Sbit (OVR, 0xC4, 5);
Sbit (MODF, 0xC4, 4);
Sbit (SPTE, 0xC4, 3);
Sbit (UARTM, 0xC4, 2);
Sbit (SPTEIE, 0xC4, 1);
Sbit (MODFIE, 0xC4, 0);

Sfr (SPDAT, 0xC5);

Sbit (SPD7, 0xC5, 7);
Sbit (SPD6, 0xC5, 6);
Sbit (SPD5, 0xC5, 5);
Sbit (SPD4, 0xC5, 4);
Sbit (SPD3, 0xC5, 3);
Sbit (SPD2, 0xC5, 2);
Sbit (SPD1, 0xC5, 1);
Sbit (SPD0, 0xC5, 0);

/*                             Keyboard Interface SFRs                                */

Sfr (KBLS, 0x9C);

Sbit (KBLS7, 0x9C, 7);
Sbit (KBLS6, 0x9C, 6);
Sbit (KBLS5, 0x9C, 5);
Sbit (KBLS4, 0x9C, 4);
Sbit (KBLS3, 0x9C, 3);
Sbit (KBLS2, 0x9C, 2);
Sbit (KBLS1, 0x9C, 1);
Sbit (KBLS0, 0x9C, 0);

Sfr (KBE, 0x9D);

Sbit (KBE0, 0x9D, 0);
Sbit (KBE1, 0x9D, 1);
Sbit (KBE2, 0x9D, 2);
Sbit (KBE3, 0x9D, 3);
Sbit (KBE4, 0x9D, 4);
Sbit (KBE5, 0x9D, 5);
Sbit (KBE6, 0x9D, 6);
Sbit (KBE7, 0x9D, 7);

Sfr (KBF, 0x9E);

Sbit (KBF7, 0x9E, 7);
Sbit (KBF6, 0x9E, 6);
Sbit (KBF5, 0x9E, 5);
Sbit (KBF4, 0x9E, 4);
Sbit (KBF3, 0x9E, 3);
Sbit (KBF2, 0x9E, 2);
Sbit (KBF1, 0x9E, 1);
Sbit (KBF0, 0x9E, 0);

#endif

Sorry this one is before part2

/*                                   PCA SFRs                                */

Sfr (CCON, 0xD8);

Sbit (CF, 0xD8, 7);
Sbit (CR, 0xD8, 6);
Sbit (CCF4, 0xD8, 4);
Sbit (CCF3, 0xD8, 3);
Sbit (CCF2, 0xD8, 2);
Sbit (CCF1, 0xD8, 1);
Sbit (CCF0, 0xD8, 0);

Sfr (CMOD, 0xD9);

Sbit (CIDL, 0xD9, 7);
Sbit (WDTE, 0xD9, 6);
Sbit (CPS1, 0xD9, 2);
Sbit (CPS0, 0xD9, 1);
Sbit (ECF, 0xD9, 0);

Sfr (CL, 0xE9);
Sfr (CH, 0xF9);
Sfr (CCAPM0, 0xDA);

Sbit (ECOM0, 0xDA, 6);
Sbit (CAPP0, 0xDA, 5);
Sbit (CAPN0, 0xDA, 4);
Sbit (MAT0, 0xDA, 3);
Sbit (TOG0, 0xDA, 2);
Sbit (PWM0, 0xDA, 1);
Sbit (ECCF0, 0xDA, 0);

Sfr (CCAPM1, 0xDB);

Sbit (ECOM1, 0xDB, 6);
Sbit (CAPP1, 0xDB, 5);
Sbit (CAPN1, 0xDB, 4);
Sbit (MAT1, 0xDB, 3);
Sbit (TOG1, 0xDB, 2);
Sbit (PWM1, 0xDB, 1);
Sbit (ECCF1, 0xDB, 0);

Sfr (CCAPM2, 0xDC);

Sbit (ECOM2, 0xDC, 6);
Sbit (CAPP2, 0xDC, 5);
Sbit (CAPN2, 0xDC, 4);
Sbit (MAT2, 0xDC, 3);
Sbit (TOG2, 0xDC, 2);
Sbit (PWM2, 0xDC, 1);
Sbit (ECCF2, 0xDC, 0);

Sfr (CCAPM3, 0xDD);

Sbit (ECOM3, 0xDD, 6);
Sbit (CAPP3, 0xDD, 5);
Sbit (CAPN3, 0xDD, 4);
Sbit (MAT3, 0xDD, 3);
Sbit (TOG3, 0xDD, 2);
Sbit (PWM3, 0xDD, 1);
Sbit (ECCF3, 0xDD, 0);

Sfr (CCAPM4, 0xDE);

Sbit (ECOM4, 0xDE, 6);
Sbit (CAPP4, 0xDE, 5);
Sbit (CAPN4, 0xDE, 4);
Sbit (MAT4, 0xDE, 3);
Sbit (TOG4, 0xDE, 2);
Sbit (PWM4, 0xDE, 1);
Sbit (ECCF4, 0xDE, 0);

Sfr (CCAP0H, 0xFA);

Sbit (CCAP0H7, 0xFA, 7);
Sbit (CCAP0H6, 0xFA, 6);
Sbit (CCAP0H5, 0xFA, 5);
Sbit (CCAP0H4, 0xFA, 4);
Sbit (CCAP0H3, 0xFA, 3);
Sbit (CCAP0H2, 0xFA, 2);
Sbit (CCAP0H1, 0xFA, 1);
Sbit (CCAP0H0, 0xFA, 0);

Sfr (CCAP1H, 0xFB);

Sbit (CCAP1H7, 0xFB, 7);
Sbit (CCAP1H6, 0xFB, 6);
Sbit (CCAP1H5, 0xFB, 5);
Sbit (CCAP1H4, 0xFB, 4);
Sbit (CCAP1H3, 0xFB, 3);
Sbit (CCAP1H2, 0xFB, 2);
Sbit (CCAP1H1, 0xFB, 1);
Sbit (CCAP1H0, 0xFB, 0);

Sfr (CCAP2H, 0xFC);

Sbit (CCAP2H7, 0xFC, 7);
Sbit (CCAP2H6, 0xFC, 6);
Sbit (CCAP2H5, 0xFC, 5);
Sbit (CCAP2H4, 0xFC, 4);
Sbit (CCAP2H3, 0xFC, 3);
Sbit (CCAP2H2, 0xFC, 2);
Sbit (CCAP2H1, 0xFC, 1);
Sbit (CCAP2H0, 0xFC, 0);

Sfr (CCAP3H, 0xFD);

Sbit (CCAP3H7, 0xFD, 7);
Sbit (CCAP3H6, 0xFD, 6);
Sbit (CCAP3H5, 0xFD, 5);
Sbit (CCAP3H4, 0xFD, 4);
Sbit (CCAP3H3, 0xFD, 3);
Sbit (CCAP3H2, 0xFD, 2);
Sbit (CCAP3H1, 0xFD, 1);
Sbit (CCAP3H0, 0xFD, 0);

I will start checking the files immediately.

Back in 10.

can anybody check my header file please
a herculean task.

I doubt anybody will spend hours (for free) checking this enomous file against the datasheet.

New(ish) header files typically have an error or two that comes out when you are debuging. This is the way to verify a header file

I posted under the assumption that you had a compile or functional erro.

Erik

Thanks for your efforts i knew it would be cumbersome thats why i asked in first place
Anyway check it if and only if u have that much time and patients . Otherwise I'll check it once I start programming with AT89c51re2 I just thought this way it will save me some time and obviously few errors if there are.