Hi,
I'm using LPC2378 with 4 Mbits FRAM, and so I have to manage 8 banks of 64Ko (only CS0 is ised as chip select).
I wrote a test program that filled each bank with a continuous upcounting 32 bits value. But last bytes of each bank are altered: it seems the write buffer is not empty and the write is not finished when I change the bank select. So , there's a EMC Status register I want to chech before changing banks.
From the lpc2378 user manual :
EMC Status Register (EMCStatus - 0xFFE0 8004) -------------------------------------------------------------------- bit 0 : B Busy. This bit is used to ensure that the memory controller enters the low-power or disabled mode cleanly by determining if the memory controller is busy or not: 0 EMC is idle (warm reset value). 1 EMC is busy performing memory transactions, commands, auto-refresh cycles, or is in self-refresh mode (POR reset value). -------------------------------------------------------------------- bit 1 : S Write buffer status. This bit enables the EMC to enter low-power mode or disabled mode cleanly: 0 Write buffers empty (POR reset value) 1 Write buffers contain data. -------------------------------------------------------------------- bit 2: SA Self-refresh acknowledge. This bit indicates the operating mode of the EMC: 1 0 Normal mode 1 Self-refresh mode (POR reset value). --------------------------------------------------------------------
But when you read this register it's always returning 0x05 (the reset value). According th this value,the ECM is always busy and in self refresh !!! I understand self refresh means nothing for static RAM, but nowhere in the manual there's DRAM related topics ... So why there's a self refresh activated and how to disable it? And finally how can I get the status register functionnal ?
Thanks in advance .