Hello, can any body explain me the Checker board algorithm or even suggest me some website links. I found a lot of sites on Marching but not on checker board to test RAM memory, Thanks in advance
With regards,
See:
http://www.keil.com/forum/docs/thread141.asp
Incomplete algorithm names? Please specify full names and examples of what you expect the end result to be. The world is full of algorithms with similar names but intended for different problem areas.
What is "Checker board algorithm"? A generic name for one of several algorithms to optimize cost functions on a checkerboard? In what way where you planning on using this for embedded? Memory management?
What is "Marching"? Marching Cubes algorithm? That is a computer-graphics algorithm, and not something for embedded.
"The world is full of algorithms with similar names but intended for different problem areas."
Absolutely!
A "Checker board algorithm" could also easily mean an algorithm for playing the game of Checkers...
Read the original message again. In particular the part which says:
... to test RAM memory
But haven't heard a checker board or marching algorithm for testing RAM.
In the link provided by "Chris Burrows" states Checkerboard : Write 0x55 to even locations, 0xAA to odd locations. In all tests verify after all locations have been written. The checkerboard tests handle all stuck bit cases and many adjacent cell dependency cases.
Is checkerboard algorithm so simple.Read existing data, store it somewhere then write 0xAA or 0x55, read and compare. After that replace with original data. thats all.... If i am wrong, please correct me.
Your above summary does not represent a complete test.
Such a test will only verify the least significant (odd/even) address line. You may have other address lines that are stuck at zero or one. That is why the Greg Neff test has a step 3.
It does test a number of errors on data lines, but unless the test is run twice - one time 0xAA, 0x55 and one time 0x55, 0xAA will not find memory bits that can't store a zero or a one. That is why the Greg Neff test has a step 2.
The link suggestion to handle address line problems requires that you save all data before testing the RAM. It is possible to test the address lines without need to stash the full RAM contents, by specifically target address line aliasing, i.e. to write zero to all aliased locations, then write 0xFF and verify that the targeted address contains 0xFF while the aliased locations still has 0x00. Since you may have two aliased locations for each address line, such a test requires a limited number of bytes to be saved before verifying the address lines.
Another thing: Tests to check for stuck signals with resulting aliasing problems should be written specifically for the used architecture, since multiplexing of address/data or multilexing of row/column (high/low part of address) affects the possible errors. Or you can go the general case. Assuming that any data line may lock up or interfere with any address line and perform the "full" set of aliasing tests.