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FAST INTERRUPTIONS

RAV RAV Willow

Hello.

I am using the Infineon XC167CI Microcontroller and I have a very important doubt about fast interruptions.

I want to combine two different inputs to manage the same interruption. I was thinking to use fast interruptions in a ANDed or ORed mode, but I don't know how I can use them exactly.

Is there any information about that or could anybody help me?

Best regards, willow.

Parents
  • 0 in reply to RAV RAV Willow

    I can confirm (at least on the board I have) that if you use DAvE with the settings you have listed it works as I would expect.

    You need to remember the output of the OR gate is what will cause the interrupt (with the settings you have selected). So the two inputs of the OR gate are P2.8 and P1H.3 and you want an interrupt on any edge of the ORed result (the ORed output is what the XC167 will see and determine if an interrupt should be generated).

    So if you look at a truth table for your case (rising/falling edge interrupts) and if we assume both inputs start at zero (logic 0):

    P2.8 | P1H.3 | Out | status
   0 |    0  |  0  | starting point (no transition, no interrupt)
   0 |    1  |  1  | transition seen, interrupt yes
   1 |    1  |  1  | no transition, interrupt no
   1 |    0  |  1  | no transition, interrupt no
   0 |    0  |  0  | transition seen, interrupt yes
   1 |    0  |  1  | transition seen, interrupt yes
   1 |    1  |  1  | no transition, interrupt no


    Does this helps in your understanding?

    -Chris

Reply
  • 0 in reply to RAV RAV Willow

    I can confirm (at least on the board I have) that if you use DAvE with the settings you have listed it works as I would expect.

    You need to remember the output of the OR gate is what will cause the interrupt (with the settings you have selected). So the two inputs of the OR gate are P2.8 and P1H.3 and you want an interrupt on any edge of the ORed result (the ORed output is what the XC167 will see and determine if an interrupt should be generated).

    So if you look at a truth table for your case (rising/falling edge interrupts) and if we assume both inputs start at zero (logic 0):

    P2.8 | P1H.3 | Out | status
   0 |    0  |  0  | starting point (no transition, no interrupt)
   0 |    1  |  1  | transition seen, interrupt yes
   1 |    1  |  1  | no transition, interrupt no
   1 |    0  |  1  | no transition, interrupt no
   0 |    0  |  0  | transition seen, interrupt yes
   1 |    0  |  1  | transition seen, interrupt yes
   1 |    1  |  1  | no transition, interrupt no


    Does this helps in your understanding?

    -Chris

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