FAST INTERRUPTIONS

Have you reviewed the section in the system users manual concerning registers EXISEL0 and EXISEL1? When setting the EXIxSS field look to table 5-13.

Thanks, Cris, but I had yet read it.

I have tryed the next steps:

1) In Dave I have selected the FAST INTERRUPTION in P2.8 (external interruption 0) and I have selected Interrupt on any edge.
2) In source control tab I have selected the option Input from pin P2.8 (EXOIN) ORed with pin P1H.3

I have to say that I have a doubt because I don't know if I have to select the pin P1H.3 as input or not. Althought the result is the same if I choose this pin as a input or not.

Anyway, it doesn't work that I supposed, because the result is the same as if I had selected only "Input from pin P2.8".

When I did this action in DAVE this generates the next code:

  MAIN_vUnlockProtecReg();       // unlock EXISEL0
  EXISEL0        =  0x0003;      // load the external Interrupt  select
                                 // register 0

  MAIN_vUnlockProtecReg();       // unlock EXISEL1
  EXISEL1        =  0x0000;      // load the external Interrupt  select
                                 // register 1

  MAIN_vUnlockProtecReg();       // unlock EXICON
  EXICON         =  0x0003;      // load the external Interrupt control
                                 // register

I have read the manual you said to us and we discover the code is correct but the result is not the one I will expect.

Do you have any idea? Could you help me?

Thank you very much.

Willow.

Hello,

We have not solved this problem.

Any idea?

Thanks,

Willow.

I can confirm (at least on the board I have) that if you use DAvE with the settings you have listed it works as I would expect.

You need to remember the output of the OR gate is what will cause the interrupt (with the settings you have selected). So the two inputs of the OR gate are P2.8 and P1H.3 and you want an interrupt on any edge of the ORed result (the ORed output is what the XC167 will see and determine if an interrupt should be generated).

So if you look at a truth table for your case (rising/falling edge interrupts) and if we assume both inputs start at zero (logic 0):

P2.8 | P1H.3 | Out | status
   0 |    0  |  0  | starting point (no transition, no interrupt)
   0 |    1  |  1  | transition seen, interrupt yes
   1 |    1  |  1  | no transition, interrupt no
   1 |    0  |  1  | no transition, interrupt no
   0 |    0  |  0  | transition seen, interrupt yes
   1 |    0  |  1  | transition seen, interrupt yes
   1 |    1  |  1  | no transition, interrupt no

Does this helps in your understanding?

-Chris

Hello Chris,

Thank you very much. It does help us.

We had a wrong idea on how it works, so we will have to change it but we now know how to do it.

Thanks again.