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Hello,
I've installed a system timer (AT91RM9200 controller) - which runs without problems... I use this timer for several things.
Now I have critical code areas (only two lines of code) where no interrupt (of the st timer) is allowed to occur.
So (of course) I could disable the interrupts and after the critical code area I could enable the interrupts - but the problem is, that the interupt occurs only every one minute - so if I disable interrupts when the interrupt would occured in approximately 2 secs - and I need 4 sec until I could enable the interrupts again -> then I have to waite nearly one minute again that the next interupt occured... -> that's too long
Is there a possibility to know after the critical code area, if there was a interrupt (st timer)? so that the ISR is called (immediately) after the critical code area?
best regards Johannes
If you by "disable interrupts" means the global interrupt-enable flag, then you will not loose the timer interrupt (unless you disable the interrupt long enough that a second timer event gets blocked.
It is only if you disable the interrupt generation for the timer that you will loose the timer interrupt - since the interrupt flag will not be in the pending state until you enable interrupts again.
What do you do that requires a two second long critical section. Most of the time, critical sections are ns, us or possibly ms long. Anything that takes seconds are normally processed by a separate thread or by a state machine concurrently with other processing.
thanks for the fast reply...
What do you do that requires a two second long critical section
the time should only describe my problem a little bit better - the critical section includes only one if() question and set a bit to default - thats it....
If you by "disable interrupts" means the global interrupt-enable flag, then you will not loose the timer interrupt
I would use the mask register of the st timer (period interval timer) - so that the Watchdog which is using the same timer would work during the critical section too....
It is only if you disable the interrupt generation for the timer that you will loose the timer interrupt
What do you mean by interrupt generation for the timer? The timer has only a status register - if you read the PITs timer status - so you could see if a timer overflow occured since the last read.