Hello All,
My project uses an Actel fpga based Core51 implementation which is supported by the uVision system. Now the used memory is not fast enough to support this 12 Mhz 8051 implementation and appropriate wait cycles are used when accessing the different types of memory. The Core51 supports this by providing 'ack' signals for the different memory types. The question is now; how do I keep the timing of the uVision simulation working correctly. Is there a way to include these wait cycles in the simulated processor.
regards, Maarten