Hello all, My board uses the C167CS's SSC to communicate with an EEPROM. I looked at the code that drives the peripheral (and at the data sheet of the device) and there is something I don't understand: according to the data sheet, the clock signal transition must be introduced per bit of data send to the EEPROM. But the code does not explicitly do that: it assigns a byte to the transmit buffer and waits until the transmission is complete). The clock is assigned a 1 at the beginning of the transmission, 0 and the end of it. Is the clock waveform generated by hardware? Thanks in advance Cactus Blip
The SSC is a synchronous Serial Channel or in other terms a SPI peripheral. In master mode the clock is generated from/by the C167CS, and you can choose to the clock polarity and phase along with which bit of the transfer comes first MSB or LSB.
Thanks.