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I have a board where a 512KB battery backed RAM and 2 UARTs (16C550) are interfaced with the P89C51RD2.
The higher address bits, the RAM chip select and the UART chip selects are connected to P0 through an LS573 latch. The latch enable signal is from a port pin on Port1.
From the C51 documentation, I found two files: xbanking.a51 and L51_BANK.A51. The xbanking.a51 is for extended architecture device. The L51_BANK.A51 needs at least two code banks.
Is there any possible solution so that I can use far memory? Thanks and Regards Unmesh Oke
The XPAGE register has to be the register that actually controls the memory banking in your hardware. The code won't care if you set it to 30H. But unless 30H actually decodes into some address lines into your RAM, the bank switch won't actually switch banks.
Thanks Where should I write my bank switching code? Regards