Hi, all! I am estimating a chance to implement 100...200 kHz ADC equidistant sampling on ST10F269 (in continuous mode, I need it for signal processing in real-time, no OS). ADC is external and this is the AD7328 chip that is planned to be. The ADC must be connected through SPI bus, only this choice, unfortunately. As far as I am aware, PEC may be programmed to sustain the continuous transfer, and this is what I am actually want from the PEC. Further, it is ordinary way to put ADC's samples to a FIFO. That, in its turn, requires one of the PEC's pointer to be incremented. Now first limitation arises, namely PEC' pointer should be reprogrammed to avoid pointer being out-of array boundary. So, the interrupt must be serviced in order to reset pointer and this is in contradiction with continuous PEC' transfer that assumes no s/w routines exists. Again, this FIFO must be mapped to segment 0 if PEC involved, and this is also really limitation (data size). 1. My question is, am I right? 2. And what one could advise to achieve EQUIDISTANT sampling at 100 kHz? - With PEC to reduce CPU load. Solution like SPI's IRQs-base approach is the worst-case. 3. Am I right, PEC' pointers can not be programmed to organize circular buffer like in ADSP-21xx?
Thank you, your input was valuable for me. Yes, /CS has to be used with the ADC. Now, a supplementary h/w is planned to be to generate /CS autonomously from SPI' clocks coming in. Your approach is really designing. - I'd like the suggestion to use one of the PEC' channels to reload a pointer of another chahnel, that's great idea. Actually, I've come to an opinion (I will experiment) to force one PEC channel to generate SPI clocks (TX SPI) continuously and use RX interrupt of SPI to acquire ADC data. At 100 kHz and 40 MHz CPU it may come true, we'll see... Thank you.
At 100 kHz and 40 MHz CPU I have implemented low-pass filtering of the on-chip ADC data with ST10F168. The ADC was continuously scanning several channels at a rate of 100 kHz. The filtering code was written in assembly language and resided in the ADC ISR. The CPU load was around 30% at 25 MHz CPU clock. If all you need to do in the ISR is store ADC conversion results then the ISR should not take more than a few percent of CPU time at 40 MHz. Regards, - mike