Hi, all! I am estimating a chance to implement 100...200 kHz ADC equidistant sampling on ST10F269 (in continuous mode, I need it for signal processing in real-time, no OS). ADC is external and this is the AD7328 chip that is planned to be. The ADC must be connected through SPI bus, only this choice, unfortunately. As far as I am aware, PEC may be programmed to sustain the continuous transfer, and this is what I am actually want from the PEC. Further, it is ordinary way to put ADC's samples to a FIFO. That, in its turn, requires one of the PEC's pointer to be incremented. Now first limitation arises, namely PEC' pointer should be reprogrammed to avoid pointer being out-of array boundary. So, the interrupt must be serviced in order to reset pointer and this is in contradiction with continuous PEC' transfer that assumes no s/w routines exists. Again, this FIFO must be mapped to segment 0 if PEC involved, and this is also really limitation (data size). 1. My question is, am I right? 2. And what one could advise to achieve EQUIDISTANT sampling at 100 kHz? - With PEC to reduce CPU load. Solution like SPI's IRQs-base approach is the worst-case. 3. Am I right, PEC' pointers can not be programmed to organize circular buffer like in ADSP-21xx?
I can only offer some guidance and I have not used the AD7328 or the ST10 (but extensive experience with Infineon devices). So here are my thoughts. 1) It appears you have a good handle of the capabilities of the PEC. 2) Basically how elaborate do you want to get with hardware resources? Do you also need to generate the /CS from the ST10? This is not automatic with an SPI transfers so you would also need to control the rising and falling edge of the I/O pin. The SPI would also need two types of service, one to load the transfer and one to read the transfer. For example, you could imagine scenario to use CAPCOM timer 0 to initiate the equidistant conversion by generating a period with a low duty cycle (/CS to the AD7328). Use compare mode 3 so that the CC0 (P2.0) pin reset on a overflow (/CS active) and the compare event to de-select the device. The high time of the pin (CC0) is the inter-transfer delay. T2 is used to reload T3 when T3OTL transitions. T3 is configured in counter mode and needs an EXTERNAL WIRE to connect pins P3.6 to P2.0. The T2 reload value holds the size of the circular buffer you want. You configure three PEC's where one PEC is triggered on the Timer0 overflow (writes the command to the SSC TB after CC0 has gone low). The second PEC is configured to the SSC receive interrupt to write to the RAM buffer once a transfer has occurred (event should occur before the CC0 compare event happens so make sure to calculate your timing for all pieces of this puzzle). The third PEC is configured to the T2 interrupt which reloads the destination pointer address of the second PEC back to your first entry in your SSC receive buffer. 3) As far I can tell, yes you are correct.
Thank you, your input was valuable for me. Yes, /CS has to be used with the ADC. Now, a supplementary h/w is planned to be to generate /CS autonomously from SPI' clocks coming in. Your approach is really designing. - I'd like the suggestion to use one of the PEC' channels to reload a pointer of another chahnel, that's great idea. Actually, I've come to an opinion (I will experiment) to force one PEC channel to generate SPI clocks (TX SPI) continuously and use RX interrupt of SPI to acquire ADC data. At 100 kHz and 40 MHz CPU it may come true, we'll see... Thank you.
At 100 kHz and 40 MHz CPU I have implemented low-pass filtering of the on-chip ADC data with ST10F168. The ADC was continuously scanning several channels at a rate of 100 kHz. The filtering code was written in assembly language and resided in the ADC ISR. The CPU load was around 30% at 25 MHz CPU clock. If all you need to do in the ISR is store ADC conversion results then the ISR should not take more than a few percent of CPU time at 40 MHz. Regards, - mike