Speed difference between the target and the simulator

Marius, I'm with you on that one.

I use the simulator a whole lot and it works very well for me. Unless I am missing something and that I made several mistakes that magically cancel each other (that's possible), it's very accurate.

I'll assume that when you talk about "time", you refer to the time as seen in the virtual scope, or at the bottom of the registers windows, not the time of your watch (doh!...).

The fact that you see a factor 2 between actual execution and simulated time leads me to throw in my 2 cents: make sure that in your options for target, tab "target", the "clock" is set properly to your CPU clock (not crystal clock). This number is used to scale up and down the simulated time.

Steph-

Marius, I'm with you on that one.

I use the simulator a whole lot and it works very well for me. Unless I am missing something and that I made several mistakes that magically cancel each other (that's possible), it's very accurate.

I'll assume that when you talk about "time", you refer to the time as seen in the virtual scope, or at the bottom of the registers windows, not the time of your watch (doh!...).

The fact that you see a factor 2 between actual execution and simulated time leads me to throw in my 2 cents: make sure that in your options for target, tab "target", the "clock" is set properly to your CPU clock (not crystal clock). This number is used to scale up and down the simulated time.

Steph-

Hi Steph!

Yes, i'm talking about the time as seen in the virtual logic analyzer, not the time of my watch!!

I'm sure that i don't have any difference between the simulator clock and the target. I have the PLL bypassed, PLLIDIV and PLLODIV are both zero, CPSYS is also zero. More than that, i was able to measure the System Clock at port P3_P15 and it was exactly the oscilator frequency. I'm sure about this because the timer 3 is giving me an interrupt exactly when it should (in simulator and also measured on the target CPU). (The timers are using fSYS = fCPU)

I realized now that i'm using an simulator for the XC164CS ant my target controller is XC164CM (i have an older version of the C166, i can't update because my support has expired). Could be anything from here?

To add my two cents, I must disagree with your comments that the virtual logic analyzer is cycle accurate with an actual device. As stated by others, Keil has made NO claim to this. To have a cycle accurate simulator you must implement any pipeline stall, bubble, hazard, flush, cache hit and so on… Additionally, you need to account for memory access times to the different buses. If you have an interrupt the simulator will calculate the correct time, so asynchronous events are basically accurate.

Here is a simple example that will prove my point. For example change your delay call to a divide instruction. The simulator will just blindly count states/cycles independent of the type of instruction. So you see a big difference between the real device and the simulator because the real device needs 21 cycles for the divide instruction. Give it a try.

  while (1 == 1) {
    P3 = 0x0001;
    i = j / k;
    P3 = 0x0000;
  }

the simulator ain't no emulator

Erik

Hello Chris,

I tried your example, there was indeed quite a difference between the simulation and my target... I'll be more careful with the simulator results from now on... Nevertheless, it's still a very useful tool!

Steph-

Yes, I agree with you 100% the simulator is an extremely powerful tool and very useful within its operating constraints. I only wanted to caution you when comparing instruction cycle times as the correlation to a real device is not there.

Best regards,
Chris