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Speed difference between the target and the simulator

Marius Cristian Voicu

I'm trying to toggle an output pin but I have some timing differences between simulator and the target.
The following code is reporting me a factor of two between the simulator speed and the target (the simulator is faster than the what I'm measuring with an oscilloscope).

while (1 == 1)
{
LCD_RW = 0;
delay_xxms ();
LCD_RW = 1;
delay_xxms ();
}

void delay_xxms (void)
{
unsigned long int i, j;

for (j = 0; j < 0x0206; j ++)
{
for (i = 0; i < 0x00FA; i ++)
{
_nop_ ();
}
}
}

But! If I'm using a timer interrupt, I have the SAME timing on the target and the simulator (no other interrupts are enabled).

void LCD_timer (void) interrupt 0x0024
{
/* stop timer */
GPT12E_T4CON_T4R = 0;
if (LCD_RS == 0)
{
LCD_RS = 1;
}
else
{
LCD_RS = 0;
}
GPT12E_T4 = 0x00C8; /* supposed that f = 8 MHz and BPS = 00b (value after reset) */
/* clear timer flag */
GPT12E_T4IC_IR = 0;
/* start timer */
GPT12E_T4CON_T4R = 1;
}

I'm using the Infineon XC164 Controller and uVision 3 simulator. The quartz frequency in the simulator is 8MHZ, the same on the target. I have the PLL bypassed; PLLIDIV = 0, PLLODIV = 0, CPSYS = 0, no change if (WSRAM = 0 or WSRAM = 1), or if (WSFLASH = 00 or WSFLASH = 01)

What is happening here?

Parents
  • 0 in reply to Marius Cristian Voicu

    To add my two cents, I must disagree with your comments that the virtual logic analyzer is cycle accurate with an actual device. As stated by others, Keil has made NO claim to this. To have a cycle accurate simulator you must implement any pipeline stall, bubble, hazard, flush, cache hit and so on… Additionally, you need to account for memory access times to the different buses. If you have an interrupt the simulator will calculate the correct time, so asynchronous events are basically accurate.

    Here is a simple example that will prove my point. For example change your delay call to a divide instruction. The simulator will just blindly count states/cycles independent of the type of instruction. So you see a big difference between the real device and the simulator because the real device needs 21 cycles for the divide instruction. Give it a try.

      while (1 == 1) {
    P3 = 0x0001;
    i = j / k;
    P3 = 0x0000;
  }

    PS. There would be no difference in the cycle time of the XC164CS verses the XC164CM as they are the same core architecture.

Reply
  • 0 in reply to Marius Cristian Voicu

    To add my two cents, I must disagree with your comments that the virtual logic analyzer is cycle accurate with an actual device. As stated by others, Keil has made NO claim to this. To have a cycle accurate simulator you must implement any pipeline stall, bubble, hazard, flush, cache hit and so on… Additionally, you need to account for memory access times to the different buses. If you have an interrupt the simulator will calculate the correct time, so asynchronous events are basically accurate.

    Here is a simple example that will prove my point. For example change your delay call to a divide instruction. The simulator will just blindly count states/cycles independent of the type of instruction. So you see a big difference between the real device and the simulator because the real device needs 21 cycles for the divide instruction. Give it a try.

      while (1 == 1) {
    P3 = 0x0001;
    i = j / k;
    P3 = 0x0000;
  }

    PS. There would be no difference in the cycle time of the XC164CS verses the XC164CM as they are the same core architecture.

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