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CARM Thumb: question regarding code generation

Gerhard Kammerer

Hallo all,

What does the LSL/LSR Instruction ?
IAR C for ARM does not need it.

Thanks
Gerhard

*** CODE SEGMENT '?PR?DF_WriteToDataFlash?T?dataflash':
ARM COMPILER V2.00,  dataflash

 180: VOID DF_WriteToDataFlash(CHAR cData) small
00000000  B500      PUSH        {LR}
00000002  ---- Variable 'cData' assigned to Register 'R0'
 196:   SBUF = cConvTab[cData];
00000002  0601      LSL         R1,R0,#0x18 ; cData
00000004  0E09      LSR         R1,R1,#0x18 ; cData
00000006  4800      LDR         R0,=cConvTab ; cConvTab
00000008  5C41      LDRB        R1,[R0,R1]
0000000A  4800      LDR         R0,=SBUF ; SBUF
0000000C  7001      STRB        R1,[R0,#0x0] ; SBUF
 197:   _nop_();
0000000E  F7FF      BL          _nop_?T  ; T=0x0001  (1)
00000010  FFF7      BL          _nop_?T  ; T=0x0001  (2)
 198:   _nop_();
00000014  F7FF      BL          _nop_?T  ; T=0x0001  (1)
00000016  FFF4      BL          _nop_?T  ; T=0x0001  (2)
 216: }
0000001A  BC08      POP         {R3}
0000001C  4718      BX          R3
0000001E          ENDP ; 'DF_WriteToDataFlash?T'

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