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problem in interfacing external RAM

I am using P89LVRD2BN which has 768 XDATA RAM.I tried to extend my XDATA by providing external RAM through 74LS373 LATCH.
so when I am definig more XDATA variables,I am expecting the variables shuld automatically assignd the addresses in External RAM.
But these thing are not happening.
My settings are EXTRAM = 0 and AO = 0.(Reset Values)

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  • Hi,

    Have you tried setting EXTRAM bit in AURX to enable external ram?

    Mark.

  • When EXTRAM=0, core attempts to access internal XRAM with address
    specified in MOVX instruction. If address supplied with this
    instruction exceeds on-chip available XRAM, off-chip XRAM is
    going to be selected and accessed.
    When EXTRAM=1 every MOVX @Ri/@DPTR instruction targets external
    data memory by default.

    This is the thing mentioned in Datasheet.

    So,in my 1st attempt,I made EXTRAM=0,and I defined 3 buffers each fo size 500bytes.so totally 1500bytes which exceeds 768 bytes of internal XRAM.so I expect the remaining bytes must have got allocated in interfaced External RAM(OFF-CHIP XRAM).But it is not behaving like that.
    EXTRAM=1,nothing is working.

    In both the case AO = 0

  • best guess hardware
    what speed the processor
    what access time the memory
    what memory chip
    show cchematic

    Erik

  • RAM's access time is in interms of nanoseconds.
    My controller is working with 11.0592Mhz so takes 1.085microsecond for every instruction which is much much greater than RAM access time.

    schematic:
    I dont know how to upload it,but it is tradition way of expanding the RAM,like demultiplexing the lower order address/data by 74LS373 latch which is enabled and disabled by ALE,
    then directly shorting higher order address lines to RAM,
    then /RD and /WR pins of microcontroller to /OE and /WE pin of RAM.

    I dont think there is any problem in schematic and also with program.

    wht may be the problem?.

  • On the RAM data sheet do you have any additional enable pins? What RAM chip are you using? Many RAM chips have additional enable pins.
    Have you run in the simulator? Write some known data to your buffers and examine the XDATA memory area in the simulator.
    For your target debug,look at the _at_ keyword and place a single var at an address in XDATA and scope the address lines.
    Show a minimum code fragment of how you define and access you external XDATA.
    Bradford

  • I am able to access only the internal ON-CHIP RAM.

    And how do you know that? I.e. what actually happens (cloud of black smoke, oscilloscope displaying something...), if you try to use MOVX memory at a position where there's no internal memory?

    Does it work in the simulator?

  • I am using HMNR1288D RAM.It has only one chip enable pin.

    Variable intialisation:

    xdata unsigned char cCommonBuf1[500],cCommonBuf2[30];
    char xdata text[1256] _at_ 0x0800; /* array at xdata 0xE000 */
    

    so totally 1756 bytes which exceed the internal 768 bytes in ON chip RAM

    sample code:
    case 1:
    	memset(text,'a',500);
    	text[490] = 0;
    	if(!strncmp(text,"aaa",3))
    		SendByte('s');
    	else
    		SendByte('f');
    
    In simu;ator,when I am making a dry run,I am able to send 's' in my serial port.

    case 2:
    	memset(text,'a',500);
    	text[490] = 0;
    	if(!strncmp(text,"aba",3))
    		SendByte('s');
    	else
    		SendByte('f');
    In simu;ator,when I am making a dry run,I am able to send 'f' in my serial port.

    But in Real time interfacing with RAM,it is always sending 'f' to my hyperterm.

    whta is the problem?

  • But in Real time interfacing with RAM,it is always sending 'f' to my hyperterm.

    whta is the problem?


    Almost certainly your hardware. Dig out your oscilloscope, and check that your chip enable is actually getting enabled, and that the address/data lines move as expected.

  • RAM's access time is in interms of nanoseconds.
    My controller is working with 11.0592Mhz so takes 1.085microsecond for every instruction which is much much greater than RAM access time.

    these 2 numbers are NOT related, you need 70ns or better.

    Erik