My current design reflects the basic example in the help files in uvision. I current have 7 banks and one common area. I keep reading that Keil has support for 16MB of XDATA code space. But all the examples I've seen and the math I do 32 banks @64KB comes out to 2MB of code space. What am I missing to support that much XDATA code space if the hardware under the optimum conditions only permit 2MB limitations? I'd like to expand my code space to 16MB for some of the things I'm doing, but I can't seem to find any models that allow for the sizing limitation to be made larger than 2MB. Any ideas, or am I missing something? Jon? Thanks Chris
I'm assuming that I can use all the remaining port 1 and use port 3 as the R/W controls with the EA set low, correct? There are 3 ways you can do code banking. 1. Use a standard I/O port with sequential bits for the extra address lines. 2. Use an XDATA-mapped port with sequential bits for the extra address lines. 3. You can make up your own scheme and do that. It can be anything you like. However, you must code the bank selection routines. The standard 8051 /PSEN is used to read from code banked memory. There is nothing that makes it any different than other ROM accesses. A lot of this kind of thing is explained in the L51_BANK.A51 file. Have you looked at that? Also, configuration details are explained at: http://www.keil.com/support/man/docs/lx51/lx51_bk_config.htm. The following example shows 4 64K banks using user-defined bank switching: http://www.keil.com/support/man/docs/lx51/lx51_bk_example1.htm. The following example shows how to use a 256K ROM with standard port bits: http://www.keil.com/support/man/docs/lx51/lx51_bk_example4.htm. This is probably what most people do for code banking. Jon