Has anyone created a fully blown out bank switcher?

Should have mentioned that this is for the 87C51. The technology is listed as none. Sorry

" ... XDATA code space ... XDATA code space ... am I missing something?"

You seem to be missing the fundamental fact that XDATA space is entirely separate & distinct from CODE space.

"I'd like to expand my code space to 16MB ... for the 87C51"

Why??

Wouldn't it just make far more sense to use a processor with a native address space suitable for your project size?
Something ARM-based, perhaps?

Because our program at the university is using that core and is unchangable. So I'd like to create something spectacular from the modules and blocks of things that I've already done.

I wouldn't waste my time if I had another choice but in this case I need more code area for the core programming and xdata for external data input and outputs.

I am aware there is a difference between xdata and code space. My project will require quite a bit of both. Hence I want to maximize it out.

Do you have any other suggestions besides changing the core platform?

Thanks

Chris;
My PK51 version 7.50a supports 64 banks of 64K. Using uV3 with LX51
Bradford

My question ultimately is, based on that, do you have an example schematic to demostrate the busses and decoding logic? I'm trying to find the hardware side of this equation, my university has the same software, I would like to build the hardware to match it but I'm not 100% sure how to setup above the A15 lines and would like a basic idea of how to configure it before I waste my time milling out a garbage PCB.

Any help is appriciated and thanks!!

Chris

See Assembler/Utilities User's Guide (A51.PDF), Chapter 9, Bank Switching

Reinhard

I've read the book chapter 9 and the PDF which are the same thing thoroughly, it only shows 8 banks using random pins of each port. I'm assuming that I can use all the remaining port 1 and use port 3 as the R/W controls with the EA set low, correct? They don't make it clear why they selected those ports for the upper addresses in those examples, but I understand the code logic. Am I to assume that I can use all the remaining pins in this manner? Seems to make sense, I guess I'm just looking for validation by someone who has actually built one and tested it.

Either way I'll end up building something, thanks for the replies, keep em coming if you have anything more to offer.

Chris

I'm assuming that I can use all the remaining port 1 and use port 3 as the R/W controls with the EA set low, correct?

There are 3 ways you can do code banking.

1. Use a standard I/O port with sequential bits for the extra address lines.

2. Use an XDATA-mapped port with sequential bits for the extra address lines.

3. You can make up your own scheme and do that. It can be anything you like. However, you must code the bank selection routines.

The standard 8051 /PSEN is used to read from code banked memory. There is nothing that makes it any different than other ROM accesses.

A lot of this kind of thing is explained in the L51_BANK.A51 file. Have you looked at that?

Also, configuration details are explained at: http://www.keil.com/support/man/docs/lx51/lx51_bk_config.htm.

The following example shows 4 64K banks using user-defined bank switching: http://www.keil.com/support/man/docs/lx51/lx51_bk_example1.htm.

The following example shows how to use a 256K ROM with standard port bits: http://www.keil.com/support/man/docs/lx51/lx51_bk_example4.htm. This is probably what most people do for code banking.

Jon