It's my understanding that I must design my pcb to allow executing code from RAM if I want to use the KEIL source level debugger via the C16x serial port. My question is must the RAM be mapped to where the ROM normally would be (i.e., 0x00000), or can it be mapped to one of the other C16x chip selects? Is there a simple circuit that people use to manipulate the chip select CS0- to switch back & forth between ROM and RAM to allow the code to run from ROM when you don't want to use the debugger? Any help in understanding the H/W design requirements to make it possible to use the source level debugger would be greatly appreciated. Thanks, Dave