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Question regards SCL timing I've got a slave application running on a 87LPC762 clocked at 9.8 Mhz (external clock). I'm siumulating a transmission of one byte of data from slave to master. what happens is as soon as the slave receives the address from master ans go into a routine to check up the address (the micro should look up into a table and see if any of adresses he has to respond to is there) the master receves a Negative acknowldgement insted of waiting for the slave till it finishes its job. This will cause a problem. I guess the problem here is that my routine is taking more time than the SCL LOW/High time (12us for the routine while the SCL is ~5 us I guess for 100Khz I2C bus).....Is there any clue how to overcome this issue ?!!! Thanks
"I'm not an I2C guru..." Neither am I, but I had some brief experience with it some time ago "It must release SCL (letting it float high) and check whether it is high or the slave is holding it low to pace itself" Yes that's my recollection - the bus is "paced" by the slowest device on it (rather like IEEE-488/HPIB/GPIB).
You are both correct, I2C allows clock stretching. The slave can slow the master down for as long as needed. Of course your master side code should still have some "hung bus" timeout limit to prevent locking up. Not that the I2C bus lockup could be fixed if a slave just sits on the SCL line forever. I just mean that the master might go off and inform the user of a hung I2C bus.