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Question regards SCL timing I've got a slave application running on a 87LPC762 clocked at 9.8 Mhz (external clock). I'm siumulating a transmission of one byte of data from slave to master. what happens is as soon as the slave receives the address from master ans go into a routine to check up the address (the micro should look up into a table and see if any of adresses he has to respond to is there) the master receves a Negative acknowldgement insted of waiting for the slave till it finishes its job. This will cause a problem. I guess the problem here is that my routine is taking more time than the SCL LOW/High time (12us for the routine while the SCL is ~5 us I guess for 100Khz I2C bus).....Is there any clue how to overcome this issue ?!!! Thanks
Well...The solution should be what I have sent in my last reply (streching the clock low by not clearing the ATN flag the release it when the routine is covered) ...but again that's not what I see in the uVision2 simulator (Open question) ?!!!!! (....I overpassed my ptoblem as I figured out that the master clock is slow enough to make room for my address lookup routine in a clock period.)