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I had wrote on this subject last year and put the project down until now. I am having a problem when an external device sets its address lines to outputs while connected to the EZ-USB AN2125 chip at Port D. I an2125 goes into an unknown state. I am using the fast read and fast write on the an2125 and the fast write works just fine. When I attempt to do a fast read the the external device swithches to an output is when the an2125 loses control. Any help would be appreciated.
Since only the D lines (and frw, fwr) are connected between the micro and the external device, why would you expect "an external device sets its address lines to outputs" to affect the micro? From what little you have said, I am infering that the external device has its own separate muliplexed address bus, that is enabled on a fast transfer. This sounds very complicated. Is there another micro or FPGA involved?
The external device is another micro. The other lines that are used are a chip select and a data ready. We are trying to debug on the EZ-USB Devloper board. Is there a conflict between the external SRAMs or could we somehow have the Options for the Target set up wrong while trying to debug using the monitor??
We are actually working(somewhat) as a stand alone device (AN2125 connected to another micro) after flashing the hex code in using the control panel. We are not able to use the monitor as a debugging tool. Is there more information on how the debugger can be set up? Can we debug with just the AN2125 without the SRAM chips and all other parts that are on the EZ-USB development board?
The board does have a couple of IO memory map configuration swicthes to disable the mapping of the srams. Though they should not be active during a fast transfer. Let me guess at some more things. Hardware: You have the 2 micros. Their data busses are connected via some buffers or fifos and their address busses are totally independent. Symptoms: You can single step a fast write with the Keil monitor. You can not single step a fast read ( it hangs ).
We are using two micros that are directly connected between their data busses. We are not using a FIFO or buffer at this time. You are right that we can single step a fast write and not a fast read but we are also not able to stop anywhere within the program when the other micro changes from input to outputs on its data bus.
Sure looks like you have bus contention. Each micro thinks it is a bus master. I can not think of a way to do multiple fast transfers without a fifo between them.
I guess I don't understand your comment. The micros never try to send at the same time. Does the data bus on the an2125 always act like an output? The an2125 code works as a stand alone and not on the development board.
Can you send me information on how to set up the options on Target of the monitor for debugging purposes? Thank you for your help!
All I know is the data bus is not shared with I/O pins. The 2125 manual state that the 2125 is the SOLE master of the memory expansion bus. I would talk to Cypress to see if what you are doing is OK.