check the input & ouput of Triscend E5 I/O pin

"Triscend tools will place the the addresses of the registers in the file triscend.h."

Actually, that file will be called <project>.h, where <project> is the name of your FastChip Project.

You will also need to add the corresponding <project>.c to your uVision Project.

Note that FastChip v2.3.0 will truncate this to 8.3 characters

"Triscend tools will place the the addresses of the registers in the file triscend.h."

Actually, that file will be called <project>.h, where <project> is the name of your FastChip Project.

You will also need to add the corresponding <project>.c to your uVision Project.

Note that FastChip v2.3.0 will truncate this to 8.3 characters

Reserved XDATA addresses and non CSL implemented stuff are placed in a TE5_CSOC.H file.

TE5_CSOC.H

* $Id: //depot/software/FC220/include/TE5_CSOC.h#5 $ */
/***************************************************************************
 * Triscend E5 CSoC Device Common Register Definition File
 *
 * This file applies to all members of the Triscend E5 device family.
 *
 * Copyright (c) 2000, 2001 Triscend Corporation. All rights reserved.
 ***************************************************************************
 */

#ifndef _TE5_CSOC_H
#define _TE5_CSOC_H

/***************************************************************************
 * E5 SFR defintions
 ***************************************************************************
 */

/***************************************************************************
 * BYTE Registers
 ***************************************************************************
 */
/* Unused SFR locations [0x80,0xff] are available for use by a soft module. */
//sfr P0    =   0x80;   /* to be exported and implemented in CSL */
sfr SP      =   0x81;
sfr DPL     =   0x82;
sfr DPH     =   0x83;
sfr DPL1    =   0x84;
sfr DPH1    =   0x85;
sfr DPS     =   0x86;
sfr PCON    =   0x87;
sfr TCON    =   0x88;
sfr TMOD    =   0x89;
sfr TL0     =   0x8a;
sfr TL1     =   0x8b;
sfr TH0     =   0x8c;
sfr TH1     =   0x8d;
sfr CKCON   =   0x8e;
/* unused: 0x8f */
//sfr P1    =   0x90;   /* to be exported and implemented in CSL */
/* unused: [0x91,0x97] */
sfr SCON    =   0x98;

...

***************************************************************************
 * E5 Configuration Register Unit (CRU) defintions
 ***************************************************************************
 */

/* All addresses in the range [0xff00,0xffff] are reserved */
#define CMAP0_TAR	(*((unsigned char volatile xdata*) 0xff00))
#define CMAP0_ALT	(*((unsigned char volatile xdata*) 0xff01))
#define CMAP1_TAR_0	(*((unsigned char volatile xdata*) 0xff02))
#define CMAP1_TAR_1	(*((unsigned char volatile xdata*) 0xff03))
...

#ifdef TASKING_TOOLS
#   define SFR_BIT(name,location) _sfrbit name _at( location );
#   define SFR_BYTE(name,location) _sfrbyte name _at( location );
#   define CHAR_XDATA(name,location) volatile unsigned char _xdat name _at( location );
#   define CHAR_ARRAY_XDATA(name,location,size) volatile unsigned char _xdat name[size] _at( location );
#else
#   define SFR_BIT(name,location) sbit name = location;
#   define SFR_BYTE(name,location) sfr name = location;
#   define CHAR_XDATA(name,location) volatile unsigned char xdata name _at_ location;
#   define CHAR_ARRAY_XDATA(name,location,size) volatile unsigned char xdata name[size] _at_ location;
#endif
#define USE_PROJECT_FILE_MACRO

/* add <FastChip install directory>\include to the compiler include path */
#include <TE5_CSOC.h>


// ========= BEGIN SOFT MODULE REGISTER DECLARATIONS ======
    SFR_BYTE (P1,0x90)
// 
//     SELECTOR WITH USER ASSIGNED ADDRESS   
// 

// ========== END SOFT MODULE REGISTER DECLARATIONS =======

Thx all for your inputs.I really
appreciate it. Again, sincere thanks
to all.