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I'm looking to optimize an ISR written in C and wondered why version 6.21 pushes both DPTR when it doesn't use them both?
Well I'm planning on using it, but it seems I'm going to have to use it by dealing with inline assembler. I'm surprized Keil doesn't try to use it more often. In fact, I'm looking at the ASM listing for memcpy and I see something that is mildly disturbing. To switch back and forth between the DPTRs, they are incrementing the DPS (at addr 0x86) repeatedly. In the current revision of silicon, only the LSB is used, but what happens down the road if some of those other bits are used. All this code will just blow up??
I have a good contact at Cypress and he was one of the people that developed the EZUSB 8051 based devices. He told me (for the record): "I believe it's safe, since the "INC DPS" technique is recommended in the Dallas literature (Dallas invented the 4-clock cycle 8051 and added the second data pointer). The Synopsys 8051 core we used in EZ-USB is based on the Dallas architecture." So I guess my fears are put to rest!
I think some variants do have more than 2 DPTRs