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This is a general question, i'm used to using PIC's, and AVR's and not really 8051's. Do most people set the interrupts to another bank with 'using' and leave the rest of the code with the default. Just after some experienced users guidelines. Also we have an 8051 ASIC with 128k code and ram, 2 SPI's etc. I was looking at defining the resources so the compiler knows about this stuff. I'm a little confused about how the compiler would treat it. ie the 128k data is internal to the ASIC but does the compiler still have to treat it as external? thanks David
The 8051 was designed with switchable register banks mostly for the purpose of interrupts. In C51, the "using" statement in the interrupt function definition simply tells the compiler which bank to use. By default, a C51 program uses register bank 0 for the foreground process and assigns a different register bank to each interrupt priority. Given, however, the FX core 8051 can have 4 levels of interrupt priority, this would require 5 register banks if all four interrupt priorities are used. Therefore, its a good practive to limit your code to only 3 interrupt priorities. With respect to your ASIC, my guess would be that the 128K of internal RAM is likely accesses as xdata. By design, the 51 can only access 64K of xdata so your ASIC either includes a bank switch of some sort or has extended the size of DPTR. Hope this helps.
David Pleydell: "the 128k data is internal to the ASIC but does the compiler still have to treat it as external?" Yes, it does. All the Compiler "knows" about is the 8051 "core" - and, as far at that's concerned, the 128K is "external" - it still has to use MOVX etc instructions to access it. I'm using the Triscend E5 parts, which have an 8032 "core" plus programmable logic plus RAM on a single chip, so I've been through all this! http://www.triscend.com/products/e5.htm The option on uVision, "Use On-Chip XRAM" is a little misleading, as it doesn't actually do anything to control whether on- or off-chip RAM is used (that's done by Triscend's utilities) - it's just a quick way to tell the Linker how much XRAM it's got to play with. Robert Wey: "my guess would be that the 128K of internal RAM is likely accesses as xdata" Or PDATA?
You don't have to restrict yourself to just three interrupt priorities - although it may make thinks simpler if you do. If you do have more than three interrupt priorities the "top" three can make use of register banks 1, 2 and 3 by means of the using keyword. Any lower priority interrupts should not use the using keyword - these interrupts save the current register bank selection on the stack and set the current register bank to 0. Registers from bank 0 are saved on the stack as necessary. On exit, the interrupt will pop the register values from the stack (restoring bank 0 registers to their original values) and then switch to the original register bank before RETI. Saving registers on the stack and restoring them on exit is generally going to take longer than simply switching register banks. When allocating register banks for maximum efficiency, give thought to the priority of interrupts and how many registers that interrupt is likely to use.
A word of warning when debugging in uVision: The values displayed for R0-R7 (in both the Registers window and by typing "Rn" on the command line) are only ever for Bank zero!
A word of warning when debugging in uVision: The values displayed for R0-R7 (in both the Registers window and by typing "Rn" on the command line) are only ever for Bank zero! Uhhhh. What version of uVision2 are you using? I just tried this in 2.12 and the contents of the register window and the value of R0-R7 (entered on the command line) are for the selected register bank. Jon
2.14. We're using the Triscend E5 - could it be an issue with the processor support?
We're using the Triscend E5 - could it be an issue with the processor support? Simulation or target debugging using the E5 driver? Jon
Target for sure; haven't used simulation for a while, but I think it used to have the same problem?
Thanks everyone for some good comments. So any interrupts that i need fast responses to go into the banks with using command. Thats an interesting feature as other processors i've tried just use the stack. David
Not quite, once you use a register bank for an ISR at a given priority, use it for all ISR's at that same priority. Unless you manually nest interrupts, interrupts at the same priority are mutually exclusive and can safely share register banks with free abandon. The 8051 is stack based, but only for return addresses. Keil C51 is usually used in non-reentrant mode but if you enable reentrancy, you will have a stack based machine again. The reentrant stack can be in XDATA for reasonable stack depths. This type of "stack" is more common to RISC processors which use a compiler convention for the software stack frame. - Mark
Why does the same level priority interrupt have to be in the same bank. What is different between them that we cannot mix them? thanks David
Mark didn't say that you must use the same bank; he said you can safely use the same bank - so you don't need to "waste" extra banks on same-priority interrupts which can share (with the nesting proviso)