Hi everybody, I am a rookie working with Arm® Artisan® 28nm GLOBALFOUNDRIES 28SLPe Dual-Port High-Density SRAM Compiler. When I try to synthesize using compiler generated SRAM Verilog file I get errors due to unsynthesizable constructs. I believe this is because the generated Verilog file is just for simulation. The question is how can I generate the synthesizable Verilog code from the compiler? Or is there another way to synthesize it?