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GPU Cycle Usage

When profiling my shaders using Streamline, I found some odd things concerning the usage of GPU cycles (picture below).

The GPU I am testing on is a Mali T-880 (12-core), supposedly running at 650MHz. What surprises me is that within 1s only 442Mcycles are spent in the shaders, though 641Mcycles were available on the GPU.  Is there a good explanation for that (CPU is not maxed out) ?

 

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  • One second is a long time - if you zoom in to the 1ms view do you start to see a pattern emerging at the frame level (e.g. serialization of CPU and GPU execution)?

    In terms of the counter behavior you are seeing, the only thing I can think of is that the GPU is "busy" waiting for the CPU to handle an interrupt, which will count as "GPU active time" even though the GPU cannot make forward progress. There is a GPU IRQ active counter, so you should be able to measure this directly and see if it is high during the periods that shader core activity is low. It is impossible to tell from Streamline why an IRQ is not being acknowledged unfortunately (it may not even because caused by Mali or your application if another driver has masked interrupts, or the CPU which is responsible for handling the low level interrupt request is busy).

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  • One second is a long time - if you zoom in to the 1ms view do you start to see a pattern emerging at the frame level (e.g. serialization of CPU and GPU execution)?

    In terms of the counter behavior you are seeing, the only thing I can think of is that the GPU is "busy" waiting for the CPU to handle an interrupt, which will count as "GPU active time" even though the GPU cannot make forward progress. There is a GPU IRQ active counter, so you should be able to measure this directly and see if it is high during the periods that shader core activity is low. It is impossible to tell from Streamline why an IRQ is not being acknowledged unfortunately (it may not even because caused by Mali or your application if another driver has masked interrupts, or the CPU which is responsible for handling the low level interrupt request is busy).

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