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Is there any cache coherence between Mail400 and CPU

Hi all. As you know, there is cache in Mail400 and A35 seperately. Do I need to implement hardware cache coherence between them, for example, using CCI.

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Peter Harris over 2 years ago in reply to asic_xuan +2 verified

Mali-400 doesn't support the CCI hardware coherency protocols, this is only supported in the Bifrost architecture onwards. Any required cache coherency is managed manually in software by the device driver...

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0 asic_xuan over 2 years ago in reply to Peter Harris

Hi Peter, thanks a lot!
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0 asic_xuan over 2 years ago in reply to Peter Harris

Hi Peter, thanks a lot!
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