How to use DTCM in multicore ?

How to initialize global variables in DTCM's of other cores?? Can It be done by using Scatter file?? In multi-core environment usually the early initialization(scatter loading, library function initialization etc..) are done by primary core. So using scatter file It is possible to assign global variables to DTCM of core 0. But what can be the way to assign global variables to DTCM of secondary cores?? 

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  • In many Arm processors with TCM, there is also a bus slave port that another bus master (e.g. DMA controller) can connect to it to access TCM contents. For example, in Cortex-M7 processor we have a 32-bit AHB Lite interface for this feature:

    https://developer.arm.com/docs/ddi0489/latest/memory-system/ahb-slave-interface

    It is possible that a SoC design utilize this interface to allow another processor to access the TCM, but this is not a typically usage. Normally the TCMs are initialized by the software running on the local processor, and the TCMs are typically private to each core. Don't forget that the second core need to run its C startup anyway so this is not a problem.

    If there are two Cortex-M7 processors in a chip, the TCMs of the two cores will have same local physical addresses. So even if the bus interconnect utilize the AHB slave port for TCM to allow another processor to access its TCM, the bus interconnect need some additional address remapping.

    For multi-core designs you would likely to have shared memory connected by other means (e.g. using the main system AXI/AHB). You do need to take care that only one core will do the initialization of a shared data (otherwise another core might run the initialization while another core already started using the data, ending with losing data).

    regards,

    Joseph

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  • In many Arm processors with TCM, there is also a bus slave port that another bus master (e.g. DMA controller) can connect to it to access TCM contents. For example, in Cortex-M7 processor we have a 32-bit AHB Lite interface for this feature:

    https://developer.arm.com/docs/ddi0489/latest/memory-system/ahb-slave-interface

    It is possible that a SoC design utilize this interface to allow another processor to access the TCM, but this is not a typically usage. Normally the TCMs are initialized by the software running on the local processor, and the TCMs are typically private to each core. Don't forget that the second core need to run its C startup anyway so this is not a problem.

    If there are two Cortex-M7 processors in a chip, the TCMs of the two cores will have same local physical addresses. So even if the bus interconnect utilize the AHB slave port for TCM to allow another processor to access its TCM, the bus interconnect need some additional address remapping.

    For multi-core designs you would likely to have shared memory connected by other means (e.g. using the main system AXI/AHB). You do need to take care that only one core will do the initialization of a shared data (otherwise another core might run the initialization while another core already started using the data, ending with losing data).

    regards,

    Joseph

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