HI
I am using a single transfer in ahb lite in wait state.First i am write till htrans will maintain or not.
If i am using a write based read ,The write is not complete due to wait at the time ,At the time again i put a same addr in read transfer, it's possible or not.
Finally if one transfer is complete on first transfer data base,At the same time (first transfer data base) Again i am perform the another single transfer .If it's possible hoe to know the transfer is complete or not.
Hi ,
Thanks for your replay.
Colin Campbell said:For your second statement, if you are using a sequence of a write followed immediately by a read, if the write transfer data phase is extended by the slave driving HREADY low, the following read transfer address phase will be extended (stretched) until the write transfer has completed, and only then can the read transfer data phase start. So yes, this is possible, but the read transfer data phase cannot start until the preceding write transfer data phase completes.
I am using a SINGLE burst write based read transfer on the same address.If write complete goes to the idle state then start the read transfer. It's correct or not.
If correct i am using the same address on the write based read.First complete the write then goes to idle.It's the waste cycle of the idle state .Because i am using a same address on write and read.(IT;S ONLY IN SINGLE BURST)