HI
I am using a single transfer in ahb lite in wait state.First i am write till htrans will maintain or not.
If i am using a write based read ,The write is not complete due to wait at the time ,At the time again i put a same addr in read transfer, it's possible or not.
Finally if one transfer is complete on first transfer data base,At the same time (first transfer data base) Again i am perform the another single transfer .If it's possible hoe to know the transfer is complete or not.
Hello,
I'm not entirely sure I understand the scenarios you are describing, so I'll try describing a few sequences which might match what you are asking about in the hope that they answer your questions.
An AHB-lite transfer occurs in 2 phases, the address phase where HTRANS, HADDR and other control signals describing the requested data transfer are signalled, and then the data phase where the requested data transfer is performed and a response from the slave is returned. The data phase of a transfer can be extended by a slave if it de-asserts HREADY, but it can only do this if the address phase of the transfer was a NONSEQUENTIAL or SEQUENTIAL transfer. As the data phase of the current transfer coincides with the address phase of the next transfer, a wait state added to the data phase of the current transfer has the knock-on effect of stretching the next transfer data phase.
So following all of that, trying to address your first statement, if you are using a SINGLE type transfer signalled on HBURST, when HTRANS signals a NONSEQUENTIAL address phase for your write transfer, this indication will only last for one clock cycle (the address phase), and then the data phase of this SINGLE transfer starts. During the data phase of this transfer, the address phase signals will move on to whatever the next transfer requires, so will not usually remain at the same levels driven during this transfer address phase. It is likely that HTRANS will now be signalling IDLE if there were no further transfers to perform.
For your second statement, if you are using a sequence of a write followed immediately by a read, if the write transfer data phase is extended by the slave driving HREADY low, the following read transfer address phase will be extended (stretched) until the write transfer has completed, and only then can the read transfer data phase start. So yes, this is possible, but the read transfer data phase cannot start until the preceding write transfer data phase completes.
And finally, the master knows when each data phase transfer completes when the slave drives HREADY high, signalling the data on HWDATA has been sampled by the slave, or that the data on HRDATA should be sampled by the master.
The AHB-lite protocol is a pipelined bus, with address phases and data phases for transfers occurring in this pipelined manner, and it is the HREADY signal driven from the active slave that determines when each transfer data phase completes.
Hopefully my above description answers your questions.
Hi ,
Thanks for your replay.
Colin Campbell said:For your second statement, if you are using a sequence of a write followed immediately by a read, if the write transfer data phase is extended by the slave driving HREADY low, the following read transfer address phase will be extended (stretched) until the write transfer has completed, and only then can the read transfer data phase start. So yes, this is possible, but the read transfer data phase cannot start until the preceding write transfer data phase completes.
I am using a SINGLE burst write based read transfer on the same address.If write complete goes to the idle state then start the read transfer. It's correct or not.
If correct i am using the same address on the write based read.First complete the write then goes to idle.It's the waste cycle of the idle state .Because i am using a same address on write and read.(IT;S ONLY IN SINGLE BURST)