ACE-Lite

Hi Uma,

My blog gives an overview of hardware coherency fundamentals: Extended System Coherency - Part 1 - Cache Coherency Fundamentals

>> a ) Do they have inbuilt coherent caches? Can they be snooped?

It's useful at this point to clarify the difference between masters and slaves. A master will generate requests, e.g. a CPU or DMA. A Slave will respond to requests, e.g. a memory controller or memory mapped peripheral. ACE-Lite is a subset of ACE (and indeed a super-set of AXI).  ACE interfaces are for fully coherent agents, and ACE-Lite is one-way coherent or "IO-Coherent" which means it can snoop the ACE processors, but the ACE processors cannot snoop the ACE-Lite masters.

An example of an ACE-Lite master is the Mali-T880 GPU which does also include caches. However as it is only IO coherent these internal GPU caches will need to be managed by software, usually by cleaning at the end of every frame.

b) What type of ACE-Lite transactions are directed to them and what are the responses?

If we're now looking at ACE-Lite slaves this could cover two types of IP:

• A coherent interconnect, e.g. CoreLink CCI-500, has ACE-Lite slave interfaces which connect to the ACE-Lite masters (e.g. GPU). The interconnect will need to handle all of the complex coherency messaging and ensure correct ordering and serialization of requests from all the coherent masters.
• A memory controller, e.g. CoreLink DMC-400. Here the protocol is simpler, no coherency to worry about and close to an AXI slave.

For full details of the specification please look at the AMBA specification: http://www.arm.com/products/system-ip/amba-specifications.php

Thanks!

Neil.