Does anyone know if there is a list of ARM instruction set pseudo instructions?
Or better yet, an instruction list like PPC's, where there is a list of 'true instructions' with mnemonics and
another list of "simplified mnemonics" (=pseudo instructions) in terms of the "true instructions" (mnemonics).
There are 499 ARM instructions listed in ARMv7-A/R ARM and going through them one by one is quite a job.
The "true" PPC instructions are explained much like ARM instructions in ARMv7-A/R ARM, but in the
"simplified mnemonics" chapter the pseudo instructions are described like:
How many pseudo instructions (roughly) are there for Cortex-A7?
ARMv7-A/R ARM doesn't seem to make a difference.
The basic LDR/STR instructions (bits 27 - 25 = 0 1 0 or 0 1 1) are pseudo instructions and there is really
two basic "single data load/store" instructions: the immediate form and the register form.
The special LDR/STR instructions (bits 27 - 25 = 0 0 0) (LDRH, STRD, ...) are different instructions:
the instruction bits have different meanings and/or are in different places.
Also some PC-related instructions are "true", because unlike with other registers, using PC also loads
the CPSR, so it's functionally different even if the encoding bits are exactly the same.
Thanks, I copied that into a text file for later use. It will be handy when I get to the thumb instruction set.
Well, if I live old enough to get to the thumb instruction set.
On Cortex-M3 and Cortex-M4, I have a feeling that UXTB, UXTH, SXTB and SXTH are simplified versions of UBFX and SBFX, but I have not checked the disassembly.
At least in ARM instruction set they look like different instructions:
c c c c 0 1 1 1 1 1 1 w w w w w d d d d b b b b b 1 0 1 n n n n UBFX<c> <Rd>, <Rn>, #<lsb>, #<width>
c c c c 0 1 1 0 1 1 1 0 1 1 1 1 d d d d r r(0)(0)0 1 1 1 m m m m UXTB<c> <Rd>, <Rm>{, <rotation>}
c c c c 0 1 1 0 1 1 1 1 1 1 1 1 d d d d r r(0)(0)0 1 1 1 m m m m UXTH<c> <Rd>, <Rm>{, <rotation>}
Here w w w w w is width, b b b b b is lsb-bit place
rr is rotate count
Also, the ARMv7-A/R ARM has funny way of describing the encodings:
Under VORR it says:
if cmode<0> == ‘0’ || cmode<3:2> == ‘11’ then SEE VMOV (immediate);
(cmode = M M M M)
Under VMOV:
if op == ‘0’ && cmode<0> == ‘1’ && cmode<3:2> != ‘11’ then SEE VORR (immediate);
if op == ‘1’ && cmode != ‘1110’ then SEE “Related encodings”;
(op = f, cmode= M M M M)
Under VSHR:
if (L:imm6) IN “0000xxx” then SEE “Related encodings”;
(imm = x x x x x x)
The table-method can't tell these apart, so these rules are needed.
(There are no further info what the referenced "Related encodings" could be.)
Funny how things look more clear after a good sleep.
It looks like I'm getting forward with the coding (at last).
The state-related restrictions of MSR/MRS instructions are horrible, though.
They generate a lot of checking code.