CTRLSTAT = 0xffffffff

from Implementation of Serial Wire JTAG flash programming in ARM Cortex M3 Processors | Theesan's log  "Table 2.2.1 DP Register information" he given in 3:2 order i am taken in 2:3 order so

a[2:3] = 1 | 0

Parity = 1

Stop = 0

Perk = 1

in hex 0x95

To Read  CTRLSTAT 

startbit  = 1

APnDP = 0

R/W     = 1

from Implementation of Serial Wire JTAG flash programming in ARM Cortex M3 Processors | Theesan's log Table 2.2.1 DP Register information he given in 3:2 order i am taken in 2:3 order so

a[2:3] = 1 | 0

Parity = 0

Stop = 0

Perk = 1

in hex B1

from Implementation of Serial Wire JTAG flash programming in ARM Cortex M3 Processors | Theesan's log  "Table 2.2.1 DP Register information" he given in 3:2 order i am taken in 2:3 order so

a[2:3] = 1 | 0

Parity = 1

Stop = 0

Perk = 1

in hex 0x95

To Read  CTRLSTAT 

startbit  = 1

APnDP = 0

R/W     = 1

from Implementation of Serial Wire JTAG flash programming in ARM Cortex M3 Processors | Theesan's log Table 2.2.1 DP Register information he given in 3:2 order i am taken in 2:3 order so

a[2:3] = 1 | 0

Parity = 0

Stop = 0

Perk = 1

in hex B1

HardwareDebugConnections - ** Code Red Support Site **

from the above url i connected host GPIO to SWCLK pin of target with 10k pull down, and host GPIO to SWDIO pin of target with 10K pullup. is there any wrong with hardware connection??

The timing information can be found on the ARM Information Center under SWD timing requirements.

Each edge should be between 10 ns and 500 us.

That means ... If you're running at 168MHz: at least 2 clock cycles (one for writing, one for delay), maximum 84000 clock cycles.

I think you can use something like this, in order to get the fastest possible transfer rate at 168MHz:

#define SW_NOP      __NOP()

#define SWDIO_HI    /* replace this comment with a way to set the SWDIO pin high */

#define SWDIO_LO    /* replace this comment with a way to set the SWDIO pin low */

#define SWDIO_IN    /* replace this comment with a way to read the SWDIO pin; the value should be either 1 or 0 */

#define SWDIO_(b)   if(b){ SWDIO_HI; } else { SWDIO_LO; }

#define WR(b)       SWDIO_(b) ; SWCLK_LO ; SW_NOP         ; SWCLK_HI

#define WR1         SWDIO_HI  ; SWCLK_LO ; SW_NOP         ; SWCLK_HI

#define WR0         SWDIO_LO  ; SWCLK_LO ; SW_NOP         ; SWCLK_HI

#define RD          SW_NOP    ; SWCLK_LO ; bit = SWDIO_IN ; SW_CLK_HI

#define CLK         SW_NOP    ; SWCLK_LO ; SW_NOP         ; SWCLK_HI

The CLK macro can be used to repeat a bit; eg. if you know you're outputting 8 zero bits, you can issue WR0; CLK; CLK; CLK; CLK; CLK; CLK; CLK.

Note: The order of reading and writing must match exactly, and the high and low states on the clock must also be exact.

(That does not mean that I've written the above code correctly, though).

The WR1 would take one clock cycle, if it's translated into a STR instruction without loading register values first.

The WR0 would also take one clock cycle (same case).

The RD might take two or three clock cycles, because it's often necessary to perform a bitwise AND operation before using a bitwise OR operation to insert the new bit into a register.

The assembly code would usually look like this:

                    ldr                 r2,[r3]             /* [2] read the pin state */

                    and                 r2,r1,r2,lsr#4      /* [1] move bit 4 to bit 0 and isolate it, so it's now either 0 or 1 /*

                    add                 r0,r2,r0,ror#1      /* [1] shift the result right by 1, then insert the new bit */

Using the above mehtod means that after receiving all the bits, you'd need to rotate the entire result left by the number of bits received -  1.

Note: on Cortex-M4, the BFX instruction can also be used for extracting the bit.

-But in some cases, you might be able to read from a port, where the bit value will always be 1 or 0.

-But also according to the documentation found here, there should be turnaround: http://www.arm.com/files/pdf/Low_Pin-Count_Debug_Interfaces_for_Multi-device_Systems.pdf

I get IDCODE 0x2BA01477 for both STM32F4 (which is a Cortex-M4 device) and LPC1751 (which is a Cortex-M3 device).

Here's a similar session with JTAG-lock-pick Tiny 2 and LPC1751:

11111111111111111111111111111111111111111111111111011110011110011111111111111111

11111111111111111111111111111111111100101001011001110111000101000000001011101010

00111000000110011011110000000000000000000000000000000000001011000110010000010000

00000000000000000111101110010101100110000010000000000000000000000000011011000110

00000001000000000000000000000000011110010101100110000000000000000000000000000101

In both cases, it seems there's no turnaround clock. So I believe that right after sending the last bit, before changing the SWCLK to LOW, you could try and change the SWDIO direction to input, then issue the SWCLK_LO and have 0 turn-around clock cycles.

According to all the documents I found, it seems that data are sampled on the rising edge of SWCLK, thus changing the direction should be done right after you've sampled the data.

So far, I have been unable to do a test with the JTAG-lock-pick Tiny 2 connected to the Discovery board, but if I get it set up, I'll post the output here as well.