There's many references to Debugging a Hard Fault on Cortex-M3 & M4; eg
niallcooling's Developing a Generic Hard Fault handler for Armv7-M
https://community.freescale.com/thread/306244 - which references http://www.keil.com/appnotes/files/apnt209.pdf
But hard to find anything specifically for Cortex-M0 (or M0+)
The Armv6-M Architecture Reference Manual seems to be saying that many of the features that the above references rely upon are not provided in Cortex-M0; eg, there's no CFSR and no HFSR.
I have managed to implement a Hard Fault handler (from suggestions above), and it is called when a Hard Fault occurs - just not sure how much of the information is actually valid/useful once I'm there...
I have a basic HardFault handler for Cortex-M0 based on the code included in page 216 of your book. I have checked the flags of the xPSR register, but I do not find detailed information about the cause of the fault, such as undefined instruction, invalid state, invalid PC, unaligned memory access or divide by zero.
Does the Cortex-M0 provide this information? Is thisonly available in Cortex-M3/M4?
Thanks in advance,
Due to area constraints, the fault status registers are not available on the Cortex-M0/M0+. (The more registers inside the processor, the more power it might consume and also increase the silicon area, which affect cost). As a result, software developer will have to use the techniques I posted above to identify the issue. It is less convenient, but still work.