There's many references to Debugging a Hard Fault on Cortex-M3 & M4; eg
niallcooling's Developing a Generic Hard Fault handler for Armv7-M
also:
http://supp.iar.com/Support/?Note=23721
https://community.freescale.com/thread/306244 - which references http://www.keil.com/appnotes/files/apnt209.pdf
http://www.freertos.org/Debugging-Hard-Faults-On-Cortex-M-Microcontrollers.html
http://support.code-red-tech.com/CodeRedWiki/DebugHardFault
But hard to find anything specifically for Cortex-M0 (or M0+)
The Armv6-M Architecture Reference Manual seems to be saying that many of the features that the above references rely upon are not provided in Cortex-M0; eg, there's no CFSR and no HFSR.
I have managed to implement a Hard Fault handler (from suggestions above), and it is called when a Hard Fault occurs - just not sure how much of the information is actually valid/useful once I'm there...
Cheers,
Andy.
I have here invalid value to LR when any normal ISR was happened.
how can I know LR Value in this case to get the previous code line which was executed before this interrupt.
and why in call stack "exception Frame" appeared in a normal isr ? and where the previous call stack view before isr in call stack window?
Thanks Drew. My book has an appendix on Troubleshooting too.