There's many references to Debugging a Hard Fault on Cortex-M3 & M4; eg
niallcooling's Developing a Generic Hard Fault handler for Armv7-M
https://community.freescale.com/thread/306244 - which references http://www.keil.com/appnotes/files/apnt209.pdf
But hard to find anything specifically for Cortex-M0 (or M0+)
The Armv6-M Architecture Reference Manual seems to be saying that many of the features that the above references rely upon are not provided in Cortex-M0; eg, there's no CFSR and no HFSR.
I have managed to implement a Hard Fault handler (from suggestions above), and it is called when a Hard Fault occurs - just not sure how much of the information is actually valid/useful once I'm there...
Thanks Drew. My book has an appendix on Troubleshooting too.
If using Cortex-M0+ processor, and if the Micro Trace Buffer (MTB) is available, then the instruction trace feature allows you to view the recent execution history. Application note covering usage of MTB in Keil MDK-Arm is available on Keil website: http://www.keil.com/appnotes/docs/apnt_259.asp
In summary, when debugging HardFaults on Cortex-M0/Cortex-M0+ processors, several pieces of information are very useful:
If the SP is pointing to an invalid memory location, then you won’t be able to extract the stack frame. In these occasions, you can:
If the SP is pointing to a valid location, then you should be able to extract some useful information from the stack frame.
Faults related to memory access instructions can be caused by:
You can also get a HardFault exception if you executed SVC instruction in an exception handler with same or higher priority than the SVC priority level. The fault happened because the current context does not have the right priority level for the SVC.
I have a basic HardFault handler for Cortex-M0 based on the code included in page 216 of your book. I have checked the flags of the xPSR register, but I do not find detailed information about the cause of the fault, such as undefined instruction, invalid state, invalid PC, unaligned memory access or divide by zero.
Does the Cortex-M0 provide this information? Is thisonly available in Cortex-M3/M4?
Thanks in advance,
Due to area constraints, the fault status registers are not available on the Cortex-M0/M0+. (The more registers inside the processor, the more power it might consume and also increase the silicon area, which affect cost). As a result, software developer will have to use the techniques I posted above to identify the issue. It is less convenient, but still work.
I have here invalid value to LR when any normal ISR was happened.
how can I know LR Value in this case to get the previous code line which was executed before this interrupt.
and why in call stack "exception Frame" appeared in a normal isr ? and where the previous call stack view before isr in call stack window?