Hi Everyone,
Consider an AHB transaction in which the AHB slave signals an error response, and the AHB master decides to continue the transfer with the present slave. Following are three waveforms that depict the AHB transfer. In all the three cases the AHB slave signals error when the master tries to write to the location "WADDR3. When the slave signals an error, the master moves on with the transaction by reading the location "RADDR1" and slave responding by providing the corresponding read data "RDATA1".
Which amongst the following wave-forms are correct?
Waveform: 1
The htrans remains in the SEQ state during the error cycle.
The address "RADDR1" is captured in the second cycle of the error response (when hreadyout of the slave goes high, T5 cycle).
Waveform: 2
The address "RADDR1" is captured in the cycle after the error cycle (T6 cycle).
Waveform: 3
The htrans changes from SEQ to IDLE, when error is signalled by the slave. The htrans transitions back to NSEQ after the two error cycles.
The address "RADDR1" is assumed to be captured in the cycle after the error cycle (T6 cycle).
Thanks in advance,
Deepak
All 3 waveforms are illegal because you cannot change HWRITE (or HSIZE, HBURST, HPROT or HMASTLOCK) during a burst (so for a SEQ or BUSY step).
In each case your first read access is signalled as a SEQ step, so illegal.